AES/MASKED Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	78.215us	1	1	100.00
V1	smoke	aes_smoke	3.000s	73.193us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	68.011us	1	1	100.00
V1	csr_rw	aes_csr_rw	1.000s	73.956us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	977.897us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	479.369us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	62.494us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.000s	73.956us	1	1	100.00
		aes_csr_aliasing	3.000s	479.369us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	3.000s	73.193us	1	1	100.00
		aes_config_error	2.000s	141.648us	1	1	100.00
		aes_stress	3.000s	178.102us	1	1	100.00
V2	key_length	aes_smoke	3.000s	73.193us	1	1	100.00
		aes_config_error	2.000s	141.648us	1	1	100.00
		aes_stress	3.000s	178.102us	1	1	100.00
V2	back2back	aes_stress	3.000s	178.102us	1	1	100.00
		aes_b2b	12.000s	364.070us	1	1	100.00
V2	backpressure	aes_stress	3.000s	178.102us	1	1	100.00
V2	multi_message	aes_smoke	3.000s	73.193us	1	1	100.00
		aes_config_error	2.000s	141.648us	1	1	100.00
		aes_stress	3.000s	178.102us	1	1	100.00
		aes_alert_reset	3.000s	189.440us	1	1	100.00
V2	failure_test	aes_man_cfg_err	3.000s	109.983us	1	1	100.00
		aes_config_error	2.000s	141.648us	1	1	100.00
		aes_alert_reset	3.000s	189.440us	1	1	100.00
V2	trigger_clear_test	aes_clear	3.000s	68.347us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	329.127us	1	1	100.00
V2	reset_recovery	aes_alert_reset	3.000s	189.440us	1	1	100.00
V2	stress	aes_stress	3.000s	178.102us	1	1	100.00
V2	sideload	aes_stress	3.000s	178.102us	1	1	100.00
		aes_sideload	4.000s	78.863us	1	1	100.00
V2	deinitialization	aes_deinit	3.000s	180.409us	1	1	100.00
V2	stress_all	aes_stress_all	1.367m	4.817ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	59.661us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	125.077us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	125.077us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	68.011us	1	1	100.00
		aes_csr_rw	1.000s	73.956us	1	1	100.00
		aes_csr_aliasing	3.000s	479.369us	1	1	100.00
		aes_same_csr_outstanding	2.000s	243.407us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	68.011us	1	1	100.00
		aes_csr_rw	1.000s	73.956us	1	1	100.00
		aes_csr_aliasing	3.000s	479.369us	1	1	100.00
		aes_same_csr_outstanding	2.000s	243.407us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	6.000s	300.294us	1	1	100.00
V2S	fault_inject	aes_fi	3.000s	272.341us	1	1	100.00
		aes_control_fi	2.000s	86.489us	1	1	100.00
		aes_cipher_fi	2.000s	51.184us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	74.624us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	74.624us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	74.624us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	74.624us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	2.000s	78.689us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	871.509us	1	1	100.00
		aes_tl_intg_err	2.000s	284.867us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	284.867us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	3.000s	189.440us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	74.624us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	73.193us	1	1	100.00
		aes_stress	3.000s	178.102us	1	1	100.00
		aes_alert_reset	3.000s	189.440us	1	1	100.00
		aes_core_fi	7.000s	434.063us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	74.624us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	80.171us	1	1	100.00
		aes_stress	3.000s	178.102us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	3.000s	178.102us	1	1	100.00
		aes_sideload	4.000s	78.863us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	80.171us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	80.171us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	80.171us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	80.171us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	80.171us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.000s	178.102us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	3.000s	178.102us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	272.341us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	272.341us	1	1	100.00
		aes_control_fi	2.000s	86.489us	1	1	100.00
		aes_cipher_fi	2.000s	51.184us	1	1	100.00
		aes_ctr_fi	2.000s	46.915us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	272.341us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	272.341us	1	1	100.00
		aes_control_fi	2.000s	86.489us	1	1	100.00
		aes_cipher_fi	2.000s	51.184us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	51.184us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	272.341us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	272.341us	1	1	100.00
		aes_control_fi	2.000s	86.489us	1	1	100.00
		aes_ctr_fi	2.000s	46.915us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	272.341us	1	1	100.00
		aes_control_fi	2.000s	86.489us	1	1	100.00
		aes_cipher_fi	2.000s	51.184us	1	1	100.00
		aes_ctr_fi	2.000s	46.915us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	3.000s	189.440us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	272.341us	1	1	100.00
		aes_control_fi	2.000s	86.489us	1	1	100.00
		aes_cipher_fi	2.000s	51.184us	1	1	100.00
		aes_ctr_fi	2.000s	46.915us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	272.341us	1	1	100.00
		aes_control_fi	2.000s	86.489us	1	1	100.00
		aes_cipher_fi	2.000s	51.184us	1	1	100.00
		aes_ctr_fi	2.000s	46.915us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	272.341us	1	1	100.00
		aes_control_fi	2.000s	86.489us	1	1	100.00
		aes_ctr_fi	2.000s	46.915us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	272.341us	1	1	100.00
		aes_control_fi	2.000s	86.489us	1	1	100.00
		aes_cipher_fi	2.000s	51.184us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	27.000s	1.893ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.86910296799783593169762517438976121079675843216673131942235381040546087317858
      Line 1058, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1892924435 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 1892924435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---