DMA Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	267.718us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	4.000s	225.340us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	4.000s	253.319us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	56.287us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	60.769us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	11.000s	2.041ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	3.000s	300.292us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	46.024us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	60.769us	1	1	100.00
		dma_csr_aliasing	3.000s	300.292us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	54.000s	20.584ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	7.700m	47.510ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	3.033m	68.232ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	3.033m	68.232ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	7.700m	47.510ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	3.383m	18.965ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	3.033m	68.232ms	1	1	100.00
V2	dma_abort	dma_abort	13.000s	4.397ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.167m	9.581ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	34.041us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	13.530us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	217.798us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	217.798us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	56.287us	1	1	100.00
		dma_csr_rw	1.000s	60.769us	1	1	100.00
		dma_csr_aliasing	3.000s	300.292us	1	1	100.00
		dma_same_csr_outstanding	2.000s	83.910us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	56.287us	1	1	100.00
		dma_csr_rw	1.000s	60.769us	1	1	100.00
		dma_csr_aliasing	3.000s	300.292us	1	1	100.00
		dma_same_csr_outstanding	2.000s	83.910us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	10.000s	131.030us	1	1	100.00
		dma_generic_stress	3.383m	18.965ms	1	1	100.00
		dma_handshake_stress	3.033m	68.232ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	8.000s	321.217us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	2.000s	445.345us	1	1	100.00
		dma_sec_cm	2.000s	13.808us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.350m	7.720ms	1	1	100.00
		dma_longer_transfer	4.000s	171.478us	1	1	100.00
		dma_stress_all_with_rand_reset	7.000s	331.260us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.18548339609584406303941145629199233223443240089430564397133315665575725501605
      Line 90, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  331259808ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  331259808ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---