EDN Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.130s	31.552us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.850s	47.782us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.840s	31.256us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.140s	249.661us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.060s	32.848us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.020s	26.755us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.840s	31.256us	1	1	100.00
		edn_csr_aliasing	1.060s	32.848us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.120s	40.751us	1	1	100.00
V2	csrng_commands	edn_genbits	1.120s	40.751us	1	1	100.00
V2	genbits	edn_genbits	1.120s	40.751us	1	1	100.00
V2	interrupts	edn_intr	0.880s	20.842us	1	1	100.00
V2	alerts	edn_alert	1.090s	26.769us	1	1	100.00
V2	errs	edn_err	1.120s	24.580us	1	1	100.00
V2	disable	edn_disable	0.920s	18.235us	1	1	100.00
		edn_disable_auto_req_mode	1.280s	57.183us	1	1	100.00
V2	stress_all	edn_stress_all	3.530s	1.287ms	1	1	100.00
V2	intr_test	edn_intr_test	1.050s	13.729us	1	1	100.00
V2	alert_test	edn_alert_test	0.950s	34.086us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.450s	83.098us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.450s	83.098us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.850s	47.782us	1	1	100.00
		edn_csr_rw	0.840s	31.256us	1	1	100.00
		edn_csr_aliasing	1.060s	32.848us	1	1	100.00
		edn_same_csr_outstanding	1.180s	76.280us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.850s	47.782us	1	1	100.00
		edn_csr_rw	0.840s	31.256us	1	1	100.00
		edn_csr_aliasing	1.060s	32.848us	1	1	100.00
		edn_same_csr_outstanding	1.180s	76.280us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.590s	3.281ms	1	1	100.00
		edn_tl_intg_err	2.190s	124.605us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.100s	39.611us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.090s	26.769us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.590s	3.281ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.590s	3.281ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.590s	3.281ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.590s	3.281ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.090s	26.769us	1	1	100.00
		edn_sec_cm	6.590s	3.281ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.090s	26.769us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.190s	124.605us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.182m	4.592ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00