HMAC Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.400s 1.206ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.780s 13.732us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.690s 38.589us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.840s 5.689ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.290s 57.592us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 0.850s 69.517us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.690s 38.589us 1 1 100.00
hmac_csr_aliasing 2.290s 57.592us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 31.150s 10.291ms 1 1 100.00
V2 back_pressure hmac_back_pressure 12.760s 352.726us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.759m 5.432ms 1 1 100.00
hmac_test_sha384_vectors 7.411m 18.584ms 1 1 100.00
hmac_test_sha512_vectors 6.565m 11.159ms 1 1 100.00
hmac_test_hmac256_vectors 9.670s 692.220us 1 1 100.00
hmac_test_hmac384_vectors 10.320s 341.217us 1 1 100.00
hmac_test_hmac512_vectors 8.600s 587.185us 1 1 100.00
V2 burst_wr hmac_burst_wr 19.840s 2.286ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 11.010m 30.446ms 1 1 100.00
V2 error hmac_error 16.850s 4.996ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 39.730s 6.386ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.400s 1.206ms 1 1 100.00
hmac_long_msg 31.150s 10.291ms 1 1 100.00
hmac_back_pressure 12.760s 352.726us 1 1 100.00
hmac_datapath_stress 11.010m 30.446ms 1 1 100.00
hmac_burst_wr 19.840s 2.286ms 1 1 100.00
hmac_stress_all 5.852m 27.014ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.400s 1.206ms 1 1 100.00
hmac_long_msg 31.150s 10.291ms 1 1 100.00
hmac_back_pressure 12.760s 352.726us 1 1 100.00
hmac_datapath_stress 11.010m 30.446ms 1 1 100.00
hmac_wipe_secret 39.730s 6.386ms 1 1 100.00
hmac_test_sha256_vectors 2.759m 5.432ms 1 1 100.00
hmac_test_sha384_vectors 7.411m 18.584ms 1 1 100.00
hmac_test_sha512_vectors 6.565m 11.159ms 1 1 100.00
hmac_test_hmac256_vectors 9.670s 692.220us 1 1 100.00
hmac_test_hmac384_vectors 10.320s 341.217us 1 1 100.00
hmac_test_hmac512_vectors 8.600s 587.185us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.400s 1.206ms 1 1 100.00
hmac_long_msg 31.150s 10.291ms 1 1 100.00
hmac_back_pressure 12.760s 352.726us 1 1 100.00
hmac_datapath_stress 11.010m 30.446ms 1 1 100.00
hmac_burst_wr 19.840s 2.286ms 1 1 100.00
hmac_error 16.850s 4.996ms 1 1 100.00
hmac_wipe_secret 39.730s 6.386ms 1 1 100.00
hmac_test_sha256_vectors 2.759m 5.432ms 1 1 100.00
hmac_test_sha384_vectors 7.411m 18.584ms 1 1 100.00
hmac_test_sha512_vectors 6.565m 11.159ms 1 1 100.00
hmac_test_hmac256_vectors 9.670s 692.220us 1 1 100.00
hmac_test_hmac384_vectors 10.320s 341.217us 1 1 100.00
hmac_test_hmac512_vectors 8.600s 587.185us 1 1 100.00
hmac_stress_all 5.852m 27.014ms 1 1 100.00
V2 stress_all hmac_stress_all 5.852m 27.014ms 1 1 100.00
V2 alert_test hmac_alert_test 0.600s 29.509us 1 1 100.00
V2 intr_test hmac_intr_test 0.620s 56.915us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.720s 80.471us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.720s 80.471us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.780s 13.732us 1 1 100.00
hmac_csr_rw 0.690s 38.589us 1 1 100.00
hmac_csr_aliasing 2.290s 57.592us 1 1 100.00
hmac_same_csr_outstanding 0.950s 23.238us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.780s 13.732us 1 1 100.00
hmac_csr_rw 0.690s 38.589us 1 1 100.00
hmac_csr_aliasing 2.290s 57.592us 1 1 100.00
hmac_same_csr_outstanding 0.950s 23.238us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.880s 145.188us 1 1 100.00
hmac_tl_intg_err 2.910s 497.277us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.910s 497.277us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.400s 1.206ms 1 1 100.00
V3 stress_reset hmac_stress_reset 4.680s 655.853us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.870m 5.469ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.820s 11.116us 1 1 100.00
TOTAL 28 28 100.00