I2C Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	54.900s	3.458ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	11.040s	2.118ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.910s	24.473us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.890s	33.302us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.160s	213.974us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.360s	201.031us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.060s	112.154us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.890s	33.302us	1	1	100.00
		i2c_csr_aliasing	1.360s	201.031us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	5.720s	348.661us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	19.822m	22.198ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	33.130s	4.970ms	1	1	100.00
V2	host_override	i2c_host_override	0.920s	27.871us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.359m	4.535ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.257m	8.609ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.090s	1.003ms	1	1	100.00
		i2c_host_fifo_fmt_empty	5.470s	362.844us	1	1	100.00
		i2c_host_fifo_reset_rx	4.260s	314.294us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	34.030s	8.697ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	8.890s	1.441ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.640s	15.528us	0	1	0.00
V2	target_glitch	i2c_target_glitch	3.350s	2.416ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	23.630s	12.751ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.180s	3.892ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	9.610s	774.530us	1	1	100.00
		i2c_target_intr_smoke	3.680s	1.045ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.990s	201.890us	1	1	100.00
		i2c_target_fifo_reset_tx	1.030s	139.595us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.060s	14.405ms	1	1	100.00
		i2c_target_stress_rd	9.610s	774.530us	1	1	100.00
		i2c_target_intr_stress_wr	8.310s	12.819ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.730s	5.475ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	23.510s	2.541ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.920s	693.881us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.500s	326.887us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.490s	326.983us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.250s	134.041us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	33.130s	4.970ms	1	1	100.00
		i2c_host_perf_precise	1.860s	141.603us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	8.890s	1.441ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	0.680s	989.930ns	0	1	0.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.950s	3.855ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.170s	923.739us	1	1	100.00
		i2c_target_nack_txstretch	1.110s	695.847us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	6.210s	931.580us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.600s	1.503ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.710s	22.748us	1	1	100.00
V2	intr_test	i2c_intr_test	0.800s	17.270us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.160s	555.443us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.160s	555.443us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.910s	24.473us	1	1	100.00
		i2c_csr_rw	0.890s	33.302us	1	1	100.00
		i2c_csr_aliasing	1.360s	201.031us	1	1	100.00
		i2c_same_csr_outstanding	1.200s	70.729us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.910s	24.473us	1	1	100.00
		i2c_csr_rw	0.890s	33.302us	1	1	100.00
		i2c_csr_aliasing	1.360s	201.031us	1	1	100.00
		i2c_same_csr_outstanding	1.200s	70.729us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.240s	471.488us	1	1	100.00
		i2c_sec_cm	0.930s	158.372us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.240s	471.488us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	14.880s	3.400ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.190s	730.432us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.270s	813.455us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.21415742450760242601097916649746057034803882497086319834805964576910677071515
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 348660864 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 348660864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.31270339796160238536991200449510420400048608792631262156045411042397549834162
      Line 114, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 22198336890 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 22198336890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.81210274068703278288373004235492186027392172827649349554091893976873812736946
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  15527966 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  15527966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.35609648210936210477259000340701676752450191116755713161772437611415634180661
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 2415942943 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 2415942943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.87821530304059287363159426144047165443032024737211521532152954239325864072819
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 730432016 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 730432016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.114487987005687482122213998789220056593910562551160825180017798111087334528356
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3399732225 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3399732225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.101989298026162099215188530155102579120678959455794368434302192941246398584640
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 813454582 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 813454582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test i2c_target_tx_stretch_ctrl has 1 failures.

    • 0.i2c_target_tx_stretch_ctrl.3077337182742611718090407869105837328843034809307613462757493095558820386718
      Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.