KEYMGR_DPE Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	2.445m	16.606ms	1	1	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	0.930s	69.970us	1	1	100.00
V1	csr_rw	keymgr_dpe_csr_rw	0.790s	11.542us	1	1	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	4.540s	1.801ms	1	1	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	4.000s	136.500us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.410s	101.961us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	0.790s	11.542us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.000s	136.500us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	intr_test	keymgr_dpe_intr_test	0.810s	19.899us	1	1	100.00
V2	alert_test	keymgr_dpe_alert_test	0.880s	13.002us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	2.810s	313.982us	1	1	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	2.810s	313.982us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	0.930s	69.970us	1	1	100.00
		keymgr_dpe_csr_rw	0.790s	11.542us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.000s	136.500us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	1.780s	27.250us	1	1	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	0.930s	69.970us	1	1	100.00
		keymgr_dpe_csr_rw	0.790s	11.542us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.000s	136.500us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	1.780s	27.250us	1	1	100.00
V2		TOTAL			4	4	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	10.920s	864.410us	1	1	100.00
		keymgr_dpe_tl_intg_err	6.150s	1.941ms	1	1	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	1.580s	221.500us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	1.580s	221.500us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	1.580s	221.500us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	1.580s	221.500us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	3.970s	133.570us	1	1	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	10.920s	864.410us	1	1	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	10.920s	864.410us	1	1	100.00
V2S		TOTAL			4	4	100.00
		TOTAL			14	14	100.00