KMAC/UNMASKED Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	39.860s	4.897ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.790s	53.922us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.840s	21.867us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.430s	1.015ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.410s	906.995us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.820s	39.021us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.840s	21.867us	1	1	100.00
		kmac_csr_aliasing	3.410s	906.995us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.760s	21.968us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.050s	121.466us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	24.212m	39.656ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.246m	3.125ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.320s	2.336ms	1	1	100.00
		kmac_test_vectors_sha3_256	21.630s	2.171ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.788m	343.727ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.600s	18.125ms	1	1	100.00
		kmac_test_vectors_shake_128	23.344m	20.887ms	1	1	100.00
		kmac_test_vectors_shake_256	25.022m	244.227ms	1	1	100.00
		kmac_test_vectors_kmac	1.410s	28.040us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.720s	890.338us	1	1	100.00
V2	sideload	kmac_sideload	1.733m	7.095ms	1	1	100.00
V2	app	kmac_app	2.949m	72.602ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	32.490s	54.549ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.452m	7.091ms	1	1	100.00
V2	error	kmac_error	3.251m	8.007ms	1	1	100.00
V2	key_error	kmac_key_error	4.260s	2.056ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	31.890s	10.136ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	24.000s	5.296ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	17.240s	348.837us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	12.740s	2.239ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.340s	41.088us	1	1	100.00
V2	stress_all	kmac_stress_all	2.262m	2.442ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.680s	36.626us	1	1	100.00
V2	alert_test	kmac_alert_test	0.730s	72.877us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.940s	130.087us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.940s	130.087us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.790s	53.922us	1	1	100.00
		kmac_csr_rw	0.840s	21.867us	1	1	100.00
		kmac_csr_aliasing	3.410s	906.995us	1	1	100.00
		kmac_same_csr_outstanding	1.200s	27.124us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.790s	53.922us	1	1	100.00
		kmac_csr_rw	0.840s	21.867us	1	1	100.00
		kmac_csr_aliasing	3.410s	906.995us	1	1	100.00
		kmac_same_csr_outstanding	1.200s	27.124us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.210s	46.736us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.210s	46.736us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.210s	46.736us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.210s	46.736us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.880s	455.790us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	20.580s	8.435ms	1	1	100.00
		kmac_tl_intg_err	3.550s	366.393us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.550s	366.393us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.340s	41.088us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	39.860s	4.897ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.733m	7.095ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.210s	46.736us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	20.580s	8.435ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	20.580s	8.435ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	20.580s	8.435ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	39.860s	4.897ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.340s	41.088us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	20.580s	8.435ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	36.520s	2.150ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	39.860s	4.897ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.310m	4.132ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.11487311755295897967485200947075698945121632698200445021324949830419488418745
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10135903327 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x34b57000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10135903327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.72171858295540912501687212121766865493946829590875921372507130853137598976295
      Line 283, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4131833847 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4131833847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---