MBX Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.000m	8.675ms	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	8.000s	33.742us	1	1	100.00
V1	csr_rw	mbx_csr_rw	7.000s	31.066us	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	8.000s	872.486us	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	6.000s	37.181us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	2.000s	43.416us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	7.000s	31.066us	1	1	100.00
		mbx_csr_aliasing	6.000s	37.181us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	17.000s	521.279us	0	1	0.00
V2	mbx_max_activity	mbx_stress_zero_delays	13.000s	29.093us	0	1	0.00
V2	mbx_imbx_oob	mbx_imbx_oob	20.000s	979.149us	1	1	100.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	27.000s	1.101ms	1	1	100.00
V2	alert_test	mbx_alert_test	11.000s	37.986us	1	1	100.00
V2	intr_test	mbx_intr_test	9.000s	15.148us	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	11.000s	46.245us	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	11.000s	46.245us	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	8.000s	33.742us	1	1	100.00
		mbx_csr_rw	7.000s	31.066us	1	1	100.00
		mbx_csr_aliasing	6.000s	37.181us	1	1	100.00
		mbx_same_csr_outstanding	3.000s	63.750us	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	8.000s	33.742us	1	1	100.00
		mbx_csr_rw	7.000s	31.066us	1	1	100.00
		mbx_csr_aliasing	6.000s	37.181us	1	1	100.00
		mbx_same_csr_outstanding	3.000s	63.750us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	mbx_tl_intg_err	11.000s	76.747us	1	1	100.00
		mbx_sec_cm	11.000s	21.996us	1	1	100.00
V2S		TOTAL			2	2	100.00
		TOTAL			14	16	87.50

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed has 1 failures:

  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.80747302172031845073296310923091745003878748437035227021616348443022519953184
      Line 409, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 521278930 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
        UVM_ERROR @ 521278930 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
        UVM_INFO @ 521278930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:

  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.86428195158836974656679151331260921432605256350499425044426543871327233026184
      Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @  29092708 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @  29092708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---