RV_TIMER Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.900s	122.153us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.630s	14.901us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.740s	17.409us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.890s	61.795us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.820s	340.489us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.950s	222.614us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.740s	17.409us	1	1	100.00
		rv_timer_csr_aliasing	0.820s	340.489us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.800s	513.091us	0	1	0.00
V2	disabled	rv_timer_disabled	1.810s	4.172ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	53.570s	42.271ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	53.570s	42.271ms	1	1	100.00
V2	stress	rv_timer_stress_all	0.690s	52.883us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.640s	49.297us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.650s	54.650us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.310s	26.764us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.310s	26.764us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.630s	14.901us	1	1	100.00
		rv_timer_csr_rw	0.740s	17.409us	1	1	100.00
		rv_timer_csr_aliasing	0.820s	340.489us	1	1	100.00
		rv_timer_same_csr_outstanding	1.010s	83.720us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.630s	14.901us	1	1	100.00
		rv_timer_csr_rw	0.740s	17.409us	1	1	100.00
		rv_timer_csr_aliasing	0.820s	340.489us	1	1	100.00
		rv_timer_same_csr_outstanding	1.010s	83.720us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.950s	422.328us	1	1	100.00
		rv_timer_tl_intg_err	1.050s	95.926us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.050s	95.926us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.740s	31.362us	1	1	100.00
V3	max_value	rv_timer_max	0.820s	127.115us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	20.550s	27.928ms	1	1	100.00
V3		TOTAL			2	3	66.67
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.51374963076223378014447895628798441543809025199398201460241814980127137563526
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 127114638 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 127114638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.9283357581434590352526954877400202388665995340780359764109184633665447665343
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 513091074 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x81151f04) == 0x1
        UVM_INFO @ 513091074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---