SPI_HOST Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	14.000s	1.587ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	18.989us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	15.845us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	221.812us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	39.228us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	108.528us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	15.845us	1	1	100.00
		spi_host_csr_aliasing	1.000s	39.228us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	16.112us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	65.112us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	39.138us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	62.546us	1	1	100.00
		spi_host_error_cmd	2.000s	48.509us	1	1	100.00
		spi_host_event	5.000s	1.857ms	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	48.267us	1	1	100.00
V2	speed	spi_host_speed	2.000s	48.267us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	48.267us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	199.023us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	30.475us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	48.267us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	48.267us	1	1	100.00
V2	duplex	spi_host_smoke	14.000s	1.587ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	14.000s	1.587ms	1	1	100.00
V2	stress_all	spi_host_stress_all	2.000s	41.378us	1	1	100.00
V2	spien	spi_host_spien	2.000s	354.582us	1	1	100.00
V2	stall	spi_host_status_stall	35.000s	6.557ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	93.987us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	62.546us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	15.289us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	17.333us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	103.463us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	103.463us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	18.989us	1	1	100.00
		spi_host_csr_rw	1.000s	15.845us	1	1	100.00
		spi_host_csr_aliasing	1.000s	39.228us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	25.477us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	18.989us	1	1	100.00
		spi_host_csr_rw	1.000s	15.845us	1	1	100.00
		spi_host_csr_aliasing	1.000s	39.228us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	25.477us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	1.000s	277.412us	1	1	100.00
		spi_host_sec_cm	2.000s	43.400us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	277.412us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.717m	6.763ms	1	1	100.00
		TOTAL			26	26	100.00