SRAM_CTRL/MAIN Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.440s	12.928ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.760s	16.292us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.820s	17.076us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.390s	110.132us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.700s	16.829us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.430s	366.152us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.820s	17.076us	1	1	100.00
		sram_ctrl_csr_aliasing	0.700s	16.829us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.101m	18.319ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	57.790s	8.980ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.068m	13.541ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.818m	107.153ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	6.697m	16.080ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.829m	12.764ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.190m	81.128ms	1	1	100.00
V2	executable	sram_ctrl_executable	11.050m	51.660ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	58.550s	3.537ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.050m	32.361ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	55.360s	1.591ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.300s	726.643us	1	1	100.00
		sram_ctrl_throughput_w_readback	4.490s	3.063ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.319m	5.137ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.420s	724.637us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	35.482m	377.719ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.720s	22.218us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.690s	53.557us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.690s	53.557us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.760s	16.292us	1	1	100.00
		sram_ctrl_csr_rw	0.820s	17.076us	1	1	100.00
		sram_ctrl_csr_aliasing	0.700s	16.829us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.820s	286.575us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.760s	16.292us	1	1	100.00
		sram_ctrl_csr_rw	0.820s	17.076us	1	1	100.00
		sram_ctrl_csr_aliasing	0.700s	16.829us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.820s	286.575us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	34.220s	7.205ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.910s	3.236us	0	1	0.00
		sram_ctrl_tl_intg_err	2.010s	1.066ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.910s	3.236us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.010s	1.066ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.319m	5.137ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.319m	5.137ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.820s	17.076us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	11.050m	51.660ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	11.050m	51.660ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	11.050m	51.660ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.190m	81.128ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.220s	717.521us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	34.220s	7.205ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.070s	681.768us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.440s	12.928ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.440s	12.928ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	11.050m	51.660ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.910s	3.236us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.190m	81.128ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.910s	3.236us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.910s	3.236us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.440s	12.928ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.910s	3.236us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	25.420s	4.819ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.83898021650061108742767087014824557962008791719577725980648243011796148521314
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3236162 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3236162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---