SRAM_CTRL/RET Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	32.720s	137.263us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.860s	23.771us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.840s	16.154us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.160s	30.076us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.860s	44.982us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.080s	31.191us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.840s	16.154us	1	1	100.00
		sram_ctrl_csr_aliasing	0.860s	44.982us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.870s	13.145ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.620s	168.577us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	3.084m	30.564ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.080m	9.971ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	23.720s	546.690us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.493m	2.504ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.000s	505.529us	1	1	100.00
V2	executable	sram_ctrl_executable	12.204m	8.969ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.270s	1.238ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.901m	20.609ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	41.640s	382.169us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	48.200s	571.194us	1	1	100.00
		sram_ctrl_throughput_w_readback	45.050s	259.386us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.026m	69.091ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.030s	383.407us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	3.603m	188.303ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.810s	43.425us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.490s	48.240us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.490s	48.240us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.860s	23.771us	1	1	100.00
		sram_ctrl_csr_rw	0.840s	16.154us	1	1	100.00
		sram_ctrl_csr_aliasing	0.860s	44.982us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	16.569us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.860s	23.771us	1	1	100.00
		sram_ctrl_csr_rw	0.840s	16.154us	1	1	100.00
		sram_ctrl_csr_aliasing	0.860s	44.982us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.790s	16.569us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.680s	281.173us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.020s	21.687us	0	1	0.00
		sram_ctrl_tl_intg_err	1.250s	203.804us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.020s	21.687us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.250s	203.804us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.026m	69.091ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.026m	69.091ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.840s	16.154us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.204m	8.969ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.204m	8.969ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.204m	8.969ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.000s	505.529us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.000s	123.340us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.680s	281.173us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.060s	29.459us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	32.720s	137.263us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	32.720s	137.263us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.204m	8.969ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.020s	21.687us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.000s	505.529us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.020s	21.687us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.020s	21.687us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	32.720s	137.263us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.020s	21.687us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.080s	2.193ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.98422050047571828275169389006469601689484067255024006885985075460456788725018
      Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  21687238 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  21687238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.58475415257779180518416665883230060351194309772497248913275332613664821803713
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  31190517 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (14 [0xe] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  31190517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---