UART Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: cd42e67

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.570s	415.505us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.820s	177.336us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.740s	16.615us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.800s	347.193us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.730s	61.023us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.870s	70.736us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.740s	16.615us	1	1	100.00
		uart_csr_aliasing	0.730s	61.023us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	56.010s	82.056ms	1	1	100.00
V2	parity	uart_smoke	1.570s	415.505us	1	1	100.00
		uart_tx_rx	56.010s	82.056ms	1	1	100.00
V2	parity_error	uart_intr	31.310s	24.361ms	1	1	100.00
		uart_rx_parity_err	23.210s	43.391ms	1	1	100.00
V2	watermark	uart_tx_rx	56.010s	82.056ms	1	1	100.00
		uart_intr	31.310s	24.361ms	1	1	100.00
V2	fifo_full	uart_fifo_full	15.860s	151.111ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	14.870s	78.057ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	21.130s	18.508ms	1	1	100.00
V2	rx_frame_err	uart_intr	31.310s	24.361ms	1	1	100.00
V2	rx_break_err	uart_intr	31.310s	24.361ms	1	1	100.00
V2	rx_timeout	uart_intr	31.310s	24.361ms	1	1	100.00
V2	perf	uart_perf	1.669m	10.789ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.140s	3.539ms	1	1	100.00
V2	line_loopback	uart_loopback	3.140s	3.539ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	33.220s	24.389ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.460s	4.927ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.190s	2.124ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.670s	6.492ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.911m	98.821ms	1	1	100.00
V2	stress_all	uart_stress_all	48.750s	42.853ms	1	1	100.00
V2	alert_test	uart_alert_test	0.770s	53.851us	1	1	100.00
V2	intr_test	uart_intr_test	0.820s	30.843us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.320s	79.554us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.320s	79.554us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.820s	177.336us	1	1	100.00
		uart_csr_rw	0.740s	16.615us	1	1	100.00
		uart_csr_aliasing	0.730s	61.023us	1	1	100.00
		uart_same_csr_outstanding	0.650s	21.835us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.820s	177.336us	1	1	100.00
		uart_csr_rw	0.740s	16.615us	1	1	100.00
		uart_csr_aliasing	0.730s	61.023us	1	1	100.00
		uart_same_csr_outstanding	0.650s	21.835us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.010s	216.031us	1	1	100.00
		uart_tl_intg_err	1.200s	581.097us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.200s	581.097us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	23.720s	3.222ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00