CHIP Simulation Results

Wednesday October 01 2025 16:01:45 UTC

GitHub Revision: `cd42e67`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.208m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.208m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	57.685s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	27.089s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	25.423s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.435m	6.666ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.435m	6.666ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.435m	6.666ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	31.750s	10.220us	0	1	0.00
		chip_sw_example_manufacturer	2.418m		0	1	0.00
		chip_sw_example_concurrency	4.431m	3.991ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.205s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.890s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	11.520s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	11.520s		0	1	0.00
V1	xbar_smoke	xbar_smoke	21.060s	61.032us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.046m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.660m	7.269ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.933m	5.312ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	13.004s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	17.109s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	18.751s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	13.625s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.140s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.140s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.278m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.156m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.275m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.275m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.894m	5.577ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.105m	4.587ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.174m	15.050ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.775s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.937s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	13.632m	19.144ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.050m	6.207ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	23.827m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	23.827m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.503s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.264m	4.140ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.264m	4.140ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.905m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.037m	4.504ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.073m	5.103ms	1	1	100.00
		chip_sw_aes_idle	5.117m	6.057ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.243m	3.876ms	1	1	100.00
		chip_sw_kmac_idle	4.778m	4.659ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.656m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.718m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.366m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	15.409m	11.950ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.576s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.285s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.759s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.378s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.869s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.664s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.678s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.576s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.285s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.759s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.378s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.869s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.664s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.678s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.069s		0	1	0.00
		chip_sw_aes_enc_jitter_en	40.800s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	38.680s	10.400us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	38.860s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.500s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.546s		0	1	0.00
		chip_sw_clkmgr_jitter	5.170m	5.248ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.682m	5.410ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	15.993s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	37.640s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	40.690s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	38.290s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.100s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	36.880s	10.180us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13.567s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.656s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.008s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.006s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	21.994m	13.586ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.140m	12.371ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.264m	4.140ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.179s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.140m	12.371ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	15.147s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13.007s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.224s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.697s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	12.703s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	21.994m	13.586ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.174m	15.050ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	26.061m	20.019ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.780m	6.498ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.931m	9.767ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.603m	3.670ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	21.994m	13.586ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.090s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	13.497s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	21.994m	13.586ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.931s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.931m	9.767ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.861s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.383s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.656s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.787s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.583s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.839s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	13.497s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.823s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	18.913s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.823s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.823s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.823s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.257m	5.782ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.986s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.332s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	24.599s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.758s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.823s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.736m	8.289ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.246m	13.214ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.669s		0	1	0.00
		chip_prim_tl_access	21.076m	32.623ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.576s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.285s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.759s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.378s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.869s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.664s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.678s		0	1	0.00
		chip_rv_dm_lc_disabled	13.632m	19.144ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.602m	5.246ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	40.800s	10.180us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.571m	5.553ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.117m	6.057ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.883m	5.900ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	38.680s	10.400us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.243m	3.876ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.648m	3.998ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.722m	5.335ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	37.500s	10.160us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.736m	8.289ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.823s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	32.800s	10.140us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.359m	5.617ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.778m	4.659ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.886s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.886s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.761s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.272m	5.699ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.339s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.736m	8.289ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	38.860s	10.380us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	12.116s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.069s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.073m	5.103ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.073m	5.103ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.073m	5.103ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.887m	5.510ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.246m	13.214ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.246m	13.214ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.671m	8.810ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.546s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.669s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	21.994m	13.586ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.275m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.823s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.887m	5.510ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.736m	8.289ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.671m	8.810ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.375m	4.773ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.887m	5.510ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.736m	8.289ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.671m	8.810ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.375m	4.773ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.823s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.021s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	18.913s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.986s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.332s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	24.599s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.758s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.823s		0	1	0.00
		chip_prim_tl_access	21.076m	32.623ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	21.076m	32.623ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.573s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	13.655s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.656s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.069s		0	1	0.00
		chip_sw_aes_enc_jitter_en	40.800s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	38.680s	10.400us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	38.860s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	37.500s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.546s		0	1	0.00
		chip_sw_clkmgr_jitter	5.170m	5.248ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.361m	7.026ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.361m	7.026ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.977m	4.999ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.305m	4.234ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.882m	4.862ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.856m	4.767ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.251m	4.757ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.638m	4.022ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.375m	4.773ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	26.061m	20.019ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	26.061m	20.019ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.812m	4.454ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.727m	3.745ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.478m	5.681ms	1	1	100.00
		chip_sw_csrng_smoketest	3.107m	3.954ms	1	1	100.00
		chip_sw_gpio_smoketest	4.295m	4.628ms	1	1	100.00
		chip_sw_hmac_smoketest	4.710m	4.572ms	1	1	100.00
		chip_sw_kmac_smoketest	3.899m	4.262ms	1	1	100.00
		chip_sw_otbn_smoketest	4.447m	3.868ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.763m	5.043ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.853m	3.719ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.939m	4.803ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.882m	4.406ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.251m	3.820ms	1	1	100.00
		chip_sw_uart_smoketest	3.389m	3.718ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.464s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.205s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.046m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.312s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.567m	4.450ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.211m	4.582ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	36.570m	60.000ms	0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	4.035m	3.818ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.511s		0	1	0.00
		chip_rv_dm_lc_disabled	13.632m	19.144ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.502s		0	1	0.00
		chip_sw_lc_walkthrough_prod	16.186s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.796s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.785s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.511s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	12.988s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.206s		0	1	0.00
		rom_volatile_raw_unlock	12.551s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	12.096s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.084m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.851m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.656m	5.186ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.656m	5.186ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	11.520s		0	1	0.00
		chip_same_csr_outstanding	8.530s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	11.520s		0	1	0.00
		chip_same_csr_outstanding	8.530s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	51.780s	47.512us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.570s	13.325us	1	1	100.00
		xbar_smoke_large_delays	4.571m	2.375ms	1	1	100.00
		xbar_smoke_slow_rsp	5.357m	1.967ms	1	1	100.00
		xbar_random_zero_delays	52.810s	46.537us	1	1	100.00
		xbar_random_large_delays	4.904m	2.586ms	1	1	100.00
		xbar_random_slow_rsp	8.680m	3.023ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	45.810s	87.897us	1	1	100.00
		xbar_error_and_unmapped_addr	51.100s	104.846us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.084m	64.623us	1	1	100.00
		xbar_error_and_unmapped_addr	51.100s	104.846us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.347m	140.572us	1	1	100.00
		xbar_access_same_device_slow_rsp	37.646m	14.261ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.978m	371.411us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.050m	255.151us	1	1	100.00
		xbar_stress_all_with_error	24.699m	4.005ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	27.275m	2.452ms	1	1	100.00
		xbar_stress_all_with_reset_error	14.940m	1.495ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.991s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.024s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	14.065s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.617s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.554s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.893s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.491s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.040s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.708s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.650s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.294s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.233s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.722s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	55.263s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	54.742s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	57.275s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	56.674s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	50.121s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	45.365s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	47.188s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	50.999s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	31.107s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	21.909s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	35.911s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	35.360s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	33.759s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	28.076s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	29.151s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.547s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	20.088s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.021s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.711s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.852s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	13.960s		0	1	0.00
		rom_e2e_asm_init_dev	13.726s		0	1	0.00
		rom_e2e_asm_init_prod	12.098s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.748s		0	1	0.00
		rom_e2e_asm_init_rma	12.341s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.579s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.325s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	13.267s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.233s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.936m	4.466ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.166m	4.828ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.918s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.790s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.250s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	14.785s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	21.994m	13.586ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	22.993s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	19.745m	13.004ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.815s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.415s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.918s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.790s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.250s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.715s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.993s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.850s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.568s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.791m	15.919ms	1	1	100.00
		chip_sw_entropy_src_kat_test	4.214m	3.203ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.554m	4.772ms	1	1	100.00
		chip_plic_all_irqs_0	10.503m	6.035ms	1	1	100.00
		chip_plic_all_irqs_10	10.579m	5.761ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.286m	4.577ms	1	1	100.00
		chip_sw_dma_abort	5.461m	5.901ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.016s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.042s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.248s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.709s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.073s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.498s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.970s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.448s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	13.094s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.003s		0	1	0.00
		chip_sw_entropy_src_smoketest	5.099m	4.902ms	1	1	100.00
		chip_sw_mbx_smoketest	4.938m	4.146ms	1	1	100.00
		TOTAL			78	250	31.20

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.110751904956504346120423765902874437930687908599411802139601698042737646812518
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 130.685s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.58940037327849172938289567031307366742764284338619559666258996867157001120266
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 124.652s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.70264398260504116362219791740625744038969441097622969446837142655220937280855
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 124.167s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.42596567309955829932820538096348421386954633981304215730611398622422210921845
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 117.067s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.75471104003372392535611028032317227885720050968068423187144402045627491323675
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 120.151s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.112458528557914396926190624060017274147398975496122456539397464147736038017351
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.90075330991092427429736440432051553807250143253966899935276789120210973489516
    Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.59630313618991911691225579986579186618682371972792702192464396294108108556094
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.90241256486368907593879447132039237084213590276042851680391900009374888300453
    Line 379, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.1662276609038952687799114779781450994239476994829709796625264612987613292443
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.58531972924276018110174461085649987442048691664479504327078675429035862905728
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.45812947872079554069013964877898466031149238153818392086874077563651475520055
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.41306616472306360835857759551430112788734573062373354576870948521006334268946
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.115538015847755584695620962920051597037956562138238707134825791693676160400290
Line 432, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.565912 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.565912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.67700270523231645546217830148883002684842581900080884570012010220050594084915
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.702862 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.702862 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.16259768640299625513959272662610357046339962208991797861059069969827602798386
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.671552 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.671552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.52664413608951172546889963927442707720428453232882684795866614023418392420423
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.642617 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.642617 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.23483361416931751622732771048742160551941885382748202307771045835552286100003
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.853100 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.853100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.48943391704383430525984405241434310774308031076642945178517086559774683267853
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.477738 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.477738 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.114695481100544853979785070866645358298606072418239671906164372610745634914931
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8288.751150 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (13026106314302328918476752076458693156019051074450525217359971476649200094265402010493001701733494761976913296453053649443113189644567474664419452908821596 [0xf8b64807aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd37ee0f8f67f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 8288.751150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.32901501430719869716969457367402558133844031736042121882171832168229665208355
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5781.915428 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11839094290691662048944119483903879700919847246194817771397082137096966466867468692226414941249739041030136833680353445785099529140379519028739963871386716 [0xe20c4996aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3645af9677f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 5781.915428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.22247225204982249702736694816432741320358071891218741444885468070019384258256
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5577.136389 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h6283ad68  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h1  a_user: 'h2489f  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5577.136389 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.64858217365104990581001695793975936737370133862278273240735281823604296678686
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4587.218579 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h1487f96e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h1  a_user: 'h248ba  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4587.218579 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.48874393622023300004731189858106272278386309394936797626119419640862662790805
    Line 1364, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.14868776903662988970452764393960936591019500869331940645870526439484405306905
    Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5311.583564 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5311.583564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test chip_sw_lc_ctrl_test_locked0_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_test_locked0_to_scrap.15265903893174891001524410678206067590893642618549117006143397060524548601278
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.14273678980345968232514188491556693443448559336447817234902136132406689263741
    Line 633, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9767.451490 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9767.451490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.10619655038590947275146566929537033973943344016113941717856934614312662676204
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4999.288275 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4999.288275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.8515233744569839554432474615867375608609920038306819153127301868788374748585
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4233.867185 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4233.867185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.75303739131163117626481662354620582480984747582800190052735588517101807816107
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4139.999936 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4139.999936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.50249174970653980308491846311389323755181394080411340912359385067028636323791
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4766.595199 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4766.595199 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.110483780845323653825836715553023380925593881149832957319203160637090744822642
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.103381539993395203966609624713869541311473493186342285292244612317491733668484
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5186.171871 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5186.171871 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.85568380429042010032802753481452417951613161076505412958592030870134428546301
    Line 375, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15050.181136 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15050.181136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.23482225749119129634429626989215511196792456211561264214865895114308277610759
    Line 241, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 19144.476142 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x406d4 read out mismatch
  UVM_INFO @ 19144.476142 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.111617024584600940152200142025616467568667707622949836507686575146194374262797
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.89816215359929575825132331145736068605986659802196664739752750913219127304923
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5900.993932 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5900.993932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```