AES/MASKED Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	84.943us	1	1	100.00
V1	smoke	aes_smoke	2.000s	81.432us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	84.605us	1	1	100.00
V1	csr_rw	aes_csr_rw	2.000s	81.066us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	4.724ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	2.000s	213.744us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.000s	109.779us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	81.066us	1	1	100.00
		aes_csr_aliasing	2.000s	213.744us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	2.000s	81.432us	1	1	100.00
		aes_config_error	3.000s	112.467us	1	1	100.00
		aes_stress	4.000s	211.167us	1	1	100.00
V2	key_length	aes_smoke	2.000s	81.432us	1	1	100.00
		aes_config_error	3.000s	112.467us	1	1	100.00
		aes_stress	4.000s	211.167us	1	1	100.00
V2	back2back	aes_stress	4.000s	211.167us	1	1	100.00
		aes_b2b	8.000s	531.270us	1	1	100.00
V2	backpressure	aes_stress	4.000s	211.167us	1	1	100.00
V2	multi_message	aes_smoke	2.000s	81.432us	1	1	100.00
		aes_config_error	3.000s	112.467us	1	1	100.00
		aes_stress	4.000s	211.167us	1	1	100.00
		aes_alert_reset	2.000s	242.607us	1	1	100.00
V2	failure_test	aes_man_cfg_err	3.000s	140.356us	1	1	100.00
		aes_config_error	3.000s	112.467us	1	1	100.00
		aes_alert_reset	2.000s	242.607us	1	1	100.00
V2	trigger_clear_test	aes_clear	6.000s	391.375us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	199.612us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.000s	242.607us	1	1	100.00
V2	stress	aes_stress	4.000s	211.167us	1	1	100.00
V2	sideload	aes_stress	4.000s	211.167us	1	1	100.00
		aes_sideload	5.000s	453.726us	1	1	100.00
V2	deinitialization	aes_deinit	4.000s	1.097ms	1	1	100.00
V2	stress_all	aes_stress_all	19.000s	3.005ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	56.394us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	88.761us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	88.761us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	84.605us	1	1	100.00
		aes_csr_rw	2.000s	81.066us	1	1	100.00
		aes_csr_aliasing	2.000s	213.744us	1	1	100.00
		aes_same_csr_outstanding	1.000s	85.783us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	84.605us	1	1	100.00
		aes_csr_rw	2.000s	81.066us	1	1	100.00
		aes_csr_aliasing	2.000s	213.744us	1	1	100.00
		aes_same_csr_outstanding	1.000s	85.783us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	7.000s	296.967us	1	1	100.00
V2S	fault_inject	aes_fi	3.000s	342.963us	1	1	100.00
		aes_control_fi	1.000s	55.218us	1	1	100.00
		aes_cipher_fi	1.000s	108.415us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	204.111us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	204.111us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	204.111us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	204.111us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	2.000s	79.855us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	3.000s	744.093us	1	1	100.00
		aes_tl_intg_err	2.000s	124.134us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	124.134us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.000s	242.607us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	204.111us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.000s	81.432us	1	1	100.00
		aes_stress	4.000s	211.167us	1	1	100.00
		aes_alert_reset	2.000s	242.607us	1	1	100.00
		aes_core_fi	52.000s	10.005ms	0	1	0.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	204.111us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	118.968us	1	1	100.00
		aes_stress	4.000s	211.167us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	211.167us	1	1	100.00
		aes_sideload	5.000s	453.726us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	118.968us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	118.968us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	118.968us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	118.968us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	118.968us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	211.167us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	211.167us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	342.963us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	342.963us	1	1	100.00
		aes_control_fi	1.000s	55.218us	1	1	100.00
		aes_cipher_fi	1.000s	108.415us	1	1	100.00
		aes_ctr_fi	2.000s	125.773us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	342.963us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	342.963us	1	1	100.00
		aes_control_fi	1.000s	55.218us	1	1	100.00
		aes_cipher_fi	1.000s	108.415us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000s	108.415us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	342.963us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	342.963us	1	1	100.00
		aes_control_fi	1.000s	55.218us	1	1	100.00
		aes_ctr_fi	2.000s	125.773us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	342.963us	1	1	100.00
		aes_control_fi	1.000s	55.218us	1	1	100.00
		aes_cipher_fi	1.000s	108.415us	1	1	100.00
		aes_ctr_fi	2.000s	125.773us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.000s	242.607us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	342.963us	1	1	100.00
		aes_control_fi	1.000s	55.218us	1	1	100.00
		aes_cipher_fi	1.000s	108.415us	1	1	100.00
		aes_ctr_fi	2.000s	125.773us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	342.963us	1	1	100.00
		aes_control_fi	1.000s	55.218us	1	1	100.00
		aes_cipher_fi	1.000s	108.415us	1	1	100.00
		aes_ctr_fi	2.000s	125.773us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	342.963us	1	1	100.00
		aes_control_fi	1.000s	55.218us	1	1	100.00
		aes_ctr_fi	2.000s	125.773us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	342.963us	1	1	100.00
		aes_control_fi	1.000s	55.218us	1	1	100.00
		aes_cipher_fi	1.000s	108.415us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	30.000s	2.527ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_core_fi has 1 failures.

    • 0.aes_core_fi.54637382828296648622131727069309502112672948170898080255665390190388594162853
      Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_core_fi/latest/run.log

        UVM_FATAL @ 10004820996 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10004820996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.66229796304316845390348394779374175266585605217413696308432597854003423044732
      Line 1055, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 2527171314 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 2527171314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---