AES/UNMASKED Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	65.793us	1	1	100.00
V1	smoke	aes_smoke	3.000s	183.312us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	111.262us	1	1	100.00
V1	csr_rw	aes_csr_rw	1.000s	82.169us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	5.000s	193.897us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	258.124us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	77.708us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.000s	82.169us	1	1	100.00
		aes_csr_aliasing	3.000s	258.124us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	3.000s	183.312us	1	1	100.00
		aes_config_error	2.000s	79.113us	1	1	100.00
		aes_stress	2.000s	55.746us	1	1	100.00
V2	key_length	aes_smoke	3.000s	183.312us	1	1	100.00
		aes_config_error	2.000s	79.113us	1	1	100.00
		aes_stress	2.000s	55.746us	1	1	100.00
V2	back2back	aes_stress	2.000s	55.746us	1	1	100.00
		aes_b2b	3.000s	135.619us	1	1	100.00
V2	backpressure	aes_stress	2.000s	55.746us	1	1	100.00
V2	multi_message	aes_smoke	3.000s	183.312us	1	1	100.00
		aes_config_error	2.000s	79.113us	1	1	100.00
		aes_stress	2.000s	55.746us	1	1	100.00
		aes_alert_reset	2.000s	181.226us	1	1	100.00
V2	failure_test	aes_man_cfg_err	4.000s	136.253us	1	1	100.00
		aes_config_error	2.000s	79.113us	1	1	100.00
		aes_alert_reset	2.000s	181.226us	1	1	100.00
V2	trigger_clear_test	aes_clear	3.000s	300.342us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	4.000s	239.880us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.000s	181.226us	1	1	100.00
V2	stress	aes_stress	2.000s	55.746us	1	1	100.00
V2	sideload	aes_stress	2.000s	55.746us	1	1	100.00
		aes_sideload	2.000s	125.641us	1	1	100.00
V2	deinitialization	aes_deinit	2.000s	75.483us	1	1	100.00
V2	stress_all	aes_stress_all	11.000s	3.522ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	62.367us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	132.536us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	132.536us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	111.262us	1	1	100.00
		aes_csr_rw	1.000s	82.169us	1	1	100.00
		aes_csr_aliasing	3.000s	258.124us	1	1	100.00
		aes_same_csr_outstanding	2.000s	180.650us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	111.262us	1	1	100.00
		aes_csr_rw	1.000s	82.169us	1	1	100.00
		aes_csr_aliasing	3.000s	258.124us	1	1	100.00
		aes_same_csr_outstanding	2.000s	180.650us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	3.000s	88.037us	1	1	100.00
V2S	fault_inject	aes_fi	3.000s	116.237us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	1.000s	59.549us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	251.689us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	251.689us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	251.689us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	251.689us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	655.168us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	2.000s	692.909us	1	1	100.00
		aes_tl_intg_err	2.000s	205.707us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	205.707us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.000s	181.226us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	251.689us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	183.312us	1	1	100.00
		aes_stress	2.000s	55.746us	1	1	100.00
		aes_alert_reset	2.000s	181.226us	1	1	100.00
		aes_core_fi	3.000s	202.236us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	251.689us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	68.390us	1	1	100.00
		aes_stress	2.000s	55.746us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	2.000s	55.746us	1	1	100.00
		aes_sideload	2.000s	125.641us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	68.390us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	68.390us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	68.390us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	68.390us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	68.390us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.000s	55.746us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	2.000s	55.746us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	116.237us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	116.237us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	1.000s	59.549us	1	1	100.00
		aes_ctr_fi	2.000s	61.416us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	116.237us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	116.237us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	1.000s	59.549us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000s	59.549us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	116.237us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	116.237us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	2.000s	61.416us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	116.237us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	1.000s	59.549us	1	1	100.00
		aes_ctr_fi	2.000s	61.416us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.000s	181.226us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	116.237us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	1.000s	59.549us	1	1	100.00
		aes_ctr_fi	2.000s	61.416us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	116.237us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	1.000s	59.549us	1	1	100.00
		aes_ctr_fi	2.000s	61.416us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	116.237us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	2.000s	61.416us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	116.237us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	1.000s	59.549us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.000s	41.448us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.65351443655955147282282623686399032618113936878374258996871672403585681966532
      Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.26221093194099320158020367920767010073033159535478171094199978214566087430235
      Line 160, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  41447976 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @  41447976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---