CSRNG Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	3.000s	68.105us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	2.000s	22.560us	1	1	100.00
V1	csr_rw	csrng_csr_rw	3.000s	72.445us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	8.000s	214.534us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	2.000s	33.774us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	1.000s	26.593us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	72.445us	1	1	100.00
		csrng_csr_aliasing	2.000s	33.774us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	5.000s	157.463us	0	1	0.00
V2	alerts	csrng_alert	7.000s	145.603us	1	1	100.00
V2	err	csrng_err	3.000s	40.080us	1	1	100.00
V2	cmds	csrng_cmds	28.000s	1.203ms	1	1	100.00
V2	life cycle	csrng_cmds	28.000s	1.203ms	1	1	100.00
V2	stress_all	csrng_stress_all	10.633m	60.279ms	1	1	100.00
V2	intr_test	csrng_intr_test	2.000s	68.314us	1	1	100.00
V2	alert_test	csrng_alert_test	3.000s	14.151us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	6.000s	247.290us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	6.000s	247.290us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	2.000s	22.560us	1	1	100.00
		csrng_csr_rw	3.000s	72.445us	1	1	100.00
		csrng_csr_aliasing	2.000s	33.774us	1	1	100.00
		csrng_same_csr_outstanding	3.000s	23.131us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	2.000s	22.560us	1	1	100.00
		csrng_csr_rw	3.000s	72.445us	1	1	100.00
		csrng_csr_aliasing	2.000s	33.774us	1	1	100.00
		csrng_same_csr_outstanding	3.000s	23.131us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	4.000s	109.969us	1	1	100.00
		csrng_tl_intg_err	9.000s	256.795us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	2.000s	16.720us	1	1	100.00
		csrng_csr_rw	3.000s	72.445us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	7.000s	145.603us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	10.633m	60.279ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
		csrng_sec_cm	4.000s	109.969us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
		csrng_sec_cm	4.000s	109.969us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
		csrng_sec_cm	4.000s	109.969us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
		csrng_sec_cm	4.000s	109.969us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
		csrng_sec_cm	4.000s	109.969us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
		csrng_sec_cm	4.000s	109.969us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
		csrng_sec_cm	4.000s	109.969us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	7.000s	145.603us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	10.633m	60.279ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	7.000s	145.603us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	256.795us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
		csrng_sec_cm	4.000s	109.969us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
		csrng_sec_cm	4.000s	109.969us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	5.000s	157.463us	0	1	0.00
		csrng_err	3.000s	40.080us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.317m	5.142ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_intr_vseq] has 1 failures:
  • Test csrng_intr has 1 failures.

    • 0.csrng_intr.167628081527544728642218686120344061750875689701975392500846607103658369214
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log

        UVM_FATAL @ 157463300 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 157463300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---