DMA Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	270.725us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	4.000s	2.844ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	4.000s	1.367ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.000s	27.484us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	33.486us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	11.000s	4.146ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	159.188us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	35.140us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	33.486us	1	1	100.00
		dma_csr_aliasing	6.000s	159.188us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	31.000s	3.976ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	12.400m	190.444ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	6.983m	217.256ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	6.983m	217.256ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	12.400m	190.444ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	20.467m	943.278ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	6.983m	217.256ms	1	1	100.00
V2	dma_abort	dma_abort	6.000s	1.998ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.667m	29.727ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	38.722us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	16.107us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	1.061ms	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	1.061ms	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.000s	27.484us	1	1	100.00
		dma_csr_rw	2.000s	33.486us	1	1	100.00
		dma_csr_aliasing	6.000s	159.188us	1	1	100.00
		dma_same_csr_outstanding	2.000s	75.424us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.000s	27.484us	1	1	100.00
		dma_csr_rw	2.000s	33.486us	1	1	100.00
		dma_csr_aliasing	6.000s	159.188us	1	1	100.00
		dma_same_csr_outstanding	2.000s	75.424us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	567.364us	1	1	100.00
		dma_generic_stress	20.467m	943.278ms	1	1	100.00
		dma_handshake_stress	6.983m	217.256ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	6.000s	1.246ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	51.900us	1	1	100.00
		dma_sec_cm	2.000s	34.506us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.833m	25.065ms	1	1	100.00
		dma_longer_transfer	5.000s	217.930us	1	1	100.00
		dma_stress_all_with_rand_reset	8.000s	2.086ms	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.96978288169290083625126026185064250725058248768221328753027935461733404318241
      Line 99, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2085949482ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2085949482ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---