EDN Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.870s 25.897us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.880s 16.982us 1 1 100.00
V1 csr_rw edn_csr_rw 0.790s 53.288us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.690s 603.885us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 0.960s 35.930us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.480s 27.526us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.790s 53.288us 1 1 100.00
edn_csr_aliasing 0.960s 35.930us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.830s 70.744us 1 1 100.00
V2 csrng_commands edn_genbits 1.830s 70.744us 1 1 100.00
V2 genbits edn_genbits 1.830s 70.744us 1 1 100.00
V2 interrupts edn_intr 0.930s 20.667us 1 1 100.00
V2 alerts edn_alert 0.930s 39.060us 1 1 100.00
V2 errs edn_err 0.720s 51.003us 1 1 100.00
V2 disable edn_disable 0.830s 16.345us 1 1 100.00
edn_disable_auto_req_mode 0.980s 35.725us 1 1 100.00
V2 stress_all edn_stress_all 1.960s 875.429us 1 1 100.00
V2 intr_test edn_intr_test 0.740s 23.319us 1 1 100.00
V2 alert_test edn_alert_test 0.740s 17.960us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.000s 297.609us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.000s 297.609us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.880s 16.982us 1 1 100.00
edn_csr_rw 0.790s 53.288us 1 1 100.00
edn_csr_aliasing 0.960s 35.930us 1 1 100.00
edn_same_csr_outstanding 0.860s 75.470us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.880s 16.982us 1 1 100.00
edn_csr_rw 0.790s 53.288us 1 1 100.00
edn_csr_aliasing 0.960s 35.930us 1 1 100.00
edn_same_csr_outstanding 0.860s 75.470us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 24.440s 2.384ms 1 1 100.00
edn_tl_intg_err 1.620s 264.193us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.860s 27.704us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 0.930s 39.060us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 24.440s 2.384ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 24.440s 2.384ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 24.440s 2.384ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 24.440s 2.384ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 0.930s 39.060us 1 1 100.00
edn_sec_cm 24.440s 2.384ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 0.930s 39.060us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.620s 264.193us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets