HMAC Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.480s 1.710ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.720s 22.700us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.760s 18.764us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 6.870s 434.585us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.190s 1.512ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.160s 263.678us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.760s 18.764us 1 1 100.00
hmac_csr_aliasing 4.190s 1.512ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 43.880s 15.465ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.021m 3.004ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.530s 511.358us 1 1 100.00
hmac_test_sha384_vectors 6.138m 23.589ms 1 1 100.00
hmac_test_sha512_vectors 6.772m 14.553ms 1 1 100.00
hmac_test_hmac256_vectors 7.330s 258.320us 1 1 100.00
hmac_test_hmac384_vectors 6.540s 938.512us 1 1 100.00
hmac_test_hmac512_vectors 7.300s 229.143us 1 1 100.00
V2 burst_wr hmac_burst_wr 5.690s 548.391us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 9.073m 14.585ms 1 1 100.00
V2 error hmac_error 34.600s 2.756ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.368m 28.458ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.480s 1.710ms 1 1 100.00
hmac_long_msg 43.880s 15.465ms 1 1 100.00
hmac_back_pressure 1.021m 3.004ms 1 1 100.00
hmac_datapath_stress 9.073m 14.585ms 1 1 100.00
hmac_burst_wr 5.690s 548.391us 1 1 100.00
hmac_stress_all 8.202m 27.179ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.480s 1.710ms 1 1 100.00
hmac_long_msg 43.880s 15.465ms 1 1 100.00
hmac_back_pressure 1.021m 3.004ms 1 1 100.00
hmac_datapath_stress 9.073m 14.585ms 1 1 100.00
hmac_wipe_secret 1.368m 28.458ms 1 1 100.00
hmac_test_sha256_vectors 7.530s 511.358us 1 1 100.00
hmac_test_sha384_vectors 6.138m 23.589ms 1 1 100.00
hmac_test_sha512_vectors 6.772m 14.553ms 1 1 100.00
hmac_test_hmac256_vectors 7.330s 258.320us 1 1 100.00
hmac_test_hmac384_vectors 6.540s 938.512us 1 1 100.00
hmac_test_hmac512_vectors 7.300s 229.143us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.480s 1.710ms 1 1 100.00
hmac_long_msg 43.880s 15.465ms 1 1 100.00
hmac_back_pressure 1.021m 3.004ms 1 1 100.00
hmac_datapath_stress 9.073m 14.585ms 1 1 100.00
hmac_burst_wr 5.690s 548.391us 1 1 100.00
hmac_error 34.600s 2.756ms 1 1 100.00
hmac_wipe_secret 1.368m 28.458ms 1 1 100.00
hmac_test_sha256_vectors 7.530s 511.358us 1 1 100.00
hmac_test_sha384_vectors 6.138m 23.589ms 1 1 100.00
hmac_test_sha512_vectors 6.772m 14.553ms 1 1 100.00
hmac_test_hmac256_vectors 7.330s 258.320us 1 1 100.00
hmac_test_hmac384_vectors 6.540s 938.512us 1 1 100.00
hmac_test_hmac512_vectors 7.300s 229.143us 1 1 100.00
hmac_stress_all 8.202m 27.179ms 1 1 100.00
V2 stress_all hmac_stress_all 8.202m 27.179ms 1 1 100.00
V2 alert_test hmac_alert_test 0.620s 15.231us 1 1 100.00
V2 intr_test hmac_intr_test 0.700s 48.963us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.240s 28.896us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.240s 28.896us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.720s 22.700us 1 1 100.00
hmac_csr_rw 0.760s 18.764us 1 1 100.00
hmac_csr_aliasing 4.190s 1.512ms 1 1 100.00
hmac_same_csr_outstanding 0.970s 47.233us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.720s 22.700us 1 1 100.00
hmac_csr_rw 0.760s 18.764us 1 1 100.00
hmac_csr_aliasing 4.190s 1.512ms 1 1 100.00
hmac_same_csr_outstanding 0.970s 47.233us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.100s 51.070us 1 1 100.00
hmac_tl_intg_err 1.530s 58.038us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 1.530s 58.038us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.480s 1.710ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.900s 725.093us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.728m 16.662ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.310s 403.021us 1 1 100.00
TOTAL 28 28 100.00