I2C Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	53.140s	3.147ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.440s	999.333us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.930s	26.243us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.970s	69.390us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.870s	68.072us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.140s	33.041us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.920s	43.280us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.970s	69.390us	1	1	100.00
		i2c_csr_aliasing	1.140s	33.041us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.250s	40.921us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.243m	7.461ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	13.910s	400.846us	1	1	100.00
V2	host_override	i2c_host_override	0.970s	69.245us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.685m	10.298ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.382m	3.719ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.190s	91.965us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.390s	687.851us	1	1	100.00
		i2c_host_fifo_reset_rx	2.740s	287.996us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	44.730s	9.642ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	21.050s	3.932ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.450s	287.511us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.260s	947.241us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	3.512m	47.444ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.860s	792.654us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.940s	372.656us	1	1	100.00
		i2c_target_intr_smoke	7.080s	1.285ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.360s	144.268us	1	1	100.00
		i2c_target_fifo_reset_tx	1.260s	205.418us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	26.620s	33.265ms	1	1	100.00
		i2c_target_stress_rd	12.940s	372.656us	1	1	100.00
		i2c_target_intr_stress_wr	4.237m	20.130ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.350s	5.510ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	8.380s	1.430ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.720s	3.873ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.350s	285.901us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.740s	369.379us	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.750s	50.315us	0	1	0.00
V2	host_mode_config_perf	i2c_host_perf	13.910s	400.846us	1	1	100.00
		i2c_host_perf_precise	12.486m	23.372ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	21.050s	3.932ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.150s	94.315us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.800s	1.893ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.760s	494.518us	1	1	100.00
		i2c_target_nack_txstretch	1.360s	672.943us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	16.170s	1.105ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.740s	494.030us	1	1	100.00
V2	alert_test	i2c_alert_test	0.810s	17.324us	1	1	100.00
V2	intr_test	i2c_intr_test	0.690s	16.752us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.260s	367.935us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.260s	367.935us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.930s	26.243us	1	1	100.00
		i2c_csr_rw	0.970s	69.390us	1	1	100.00
		i2c_csr_aliasing	1.140s	33.041us	1	1	100.00
		i2c_same_csr_outstanding	0.960s	289.535us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.930s	26.243us	1	1	100.00
		i2c_csr_rw	0.970s	69.390us	1	1	100.00
		i2c_csr_aliasing	1.140s	33.041us	1	1	100.00
		i2c_same_csr_outstanding	0.960s	289.535us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	2.060s	661.769us	1	1	100.00
		i2c_sec_cm	0.980s	70.348us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.060s	661.769us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	3.490s	903.261us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.750s	179.219us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.580s	585.130us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.42533365625767530849067415266413325767157096395276934179688580773529172051889
      Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  40920902 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  40920902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.6392317982481802069568889824791413272226233068672758571581296545648618412326
      Line 114, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 7461028683 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 7461028683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.62714704066661270467192258438825613278935308696541065514421390580425635338023
      Line 100, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 903261494 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 903261494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.112425787792983573527858775159539633128086437415415034027045202835693171831170
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 585130454 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 585130454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.56998215482189481033184696236883154421817514336074962306727766481389434918288
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 947240592 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 947240592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.103484635692087939659191103051696260129792915385788723677192937443163260385621
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 179219040 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 179219040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test i2c_target_fifo_watermarks_tx has 1 failures.

    • 0.i2c_target_fifo_watermarks_tx.91304246548871629261988948829729267912776443744118668616848920163001748214429
      Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.