KEYMGR Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.360s 82.599us 1 1 100.00
V1 random keymgr_random 17.340s 1.030ms 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.800s 25.775us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.170s 56.058us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 4.800s 133.259us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 12.660s 4.593ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.520s 212.610us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.170s 56.058us 1 1 100.00
keymgr_csr_aliasing 12.660s 4.593ms 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 29.640s 1.741ms 1 1 100.00
V2 sideload keymgr_sideload 2.940s 130.128us 1 1 100.00
keymgr_sideload_kmac 2.090s 241.063us 1 1 100.00
keymgr_sideload_aes 3.850s 179.152us 1 1 100.00
keymgr_sideload_otbn 2.150s 127.651us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.280s 67.438us 1 1 100.00
V2 lc_disable keymgr_lc_disable 1.600s 28.878us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.740s 87.283us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 3.030s 181.592us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.980s 70.857us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 7.070s 570.913us 1 1 100.00
V2 stress_all keymgr_stress_all 6.230s 1.415ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.750s 25.842us 1 1 100.00
V2 alert_test keymgr_alert_test 0.770s 13.655us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.730s 130.700us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.730s 130.700us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.800s 25.775us 1 1 100.00
keymgr_csr_rw 1.170s 56.058us 1 1 100.00
keymgr_csr_aliasing 12.660s 4.593ms 1 1 100.00
keymgr_same_csr_outstanding 2.230s 232.048us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.800s 25.775us 1 1 100.00
keymgr_csr_rw 1.170s 56.058us 1 1 100.00
keymgr_csr_aliasing 12.660s 4.593ms 1 1 100.00
keymgr_same_csr_outstanding 2.230s 232.048us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
keymgr_tl_intg_err 9.000s 466.643us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 2.130s 483.217us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 2.130s 483.217us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 2.130s 483.217us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 2.130s 483.217us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 5.550s 1.359ms 1 1 100.00
V2S prim_count_check keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 9.000s 466.643us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 2.130s 483.217us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 29.640s 1.741ms 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 17.340s 1.030ms 1 1 100.00
keymgr_csr_rw 1.170s 56.058us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 17.340s 1.030ms 1 1 100.00
keymgr_csr_rw 1.170s 56.058us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 17.340s 1.030ms 1 1 100.00
keymgr_csr_rw 1.170s 56.058us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 1.600s 28.878us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.980s 70.857us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.980s 70.857us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 17.340s 1.030ms 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 9.170s 725.832us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.650s 168.352us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 1.600s 28.878us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.650s 168.352us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.650s 168.352us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.650s 168.352us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 6.250s 2.290ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.650s 168.352us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 12.930s 1.979ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00