KMAC/UNMASKED Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	36.670s	4.053ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	367.804us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.010s	149.069us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.400s	3.032ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.480s	538.392us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.640s	37.571us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.010s	149.069us	1	1	100.00
		kmac_csr_aliasing	5.480s	538.392us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.720s	60.148us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.100s	35.436us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	5.545m	16.688ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.377m	8.644ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	20.224m	34.042ms	1	1	100.00
		kmac_test_vectors_sha3_256	19.140m	68.994ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.678m	95.081ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.080s	2.022ms	1	1	100.00
		kmac_test_vectors_shake_128	23.558m	202.160ms	1	1	100.00
		kmac_test_vectors_shake_256	26.813m	89.784ms	1	1	100.00
		kmac_test_vectors_kmac	2.670s	385.295us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.080s	297.293us	1	1	100.00
V2	sideload	kmac_sideload	3.169m	11.470ms	1	1	100.00
V2	app	kmac_app	2.579m	3.734ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.461m	13.490ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.363m	18.401ms	1	1	100.00
V2	error	kmac_error	4.115m	8.751ms	1	1	100.00
V2	key_error	kmac_key_error	7.700s	1.953ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.260s	333.571us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	31.120s	9.342ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	11.050s	584.197us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	34.000s	10.954ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.630s	174.957us	1	1	100.00
V2	stress_all	kmac_stress_all	6.184m	65.520ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.730s	38.094us	1	1	100.00
V2	alert_test	kmac_alert_test	1.020s	31.303us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.290s	369.739us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.290s	369.739us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	367.804us	1	1	100.00
		kmac_csr_rw	1.010s	149.069us	1	1	100.00
		kmac_csr_aliasing	5.480s	538.392us	1	1	100.00
		kmac_same_csr_outstanding	1.210s	25.172us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	367.804us	1	1	100.00
		kmac_csr_rw	1.010s	149.069us	1	1	100.00
		kmac_csr_aliasing	5.480s	538.392us	1	1	100.00
		kmac_same_csr_outstanding	1.210s	25.172us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.970s	225.772us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.970s	225.772us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.970s	225.772us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.970s	225.772us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.390s	727.855us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	21.820s	6.941ms	1	1	100.00
		kmac_tl_intg_err	2.110s	119.419us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.110s	119.419us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.630s	174.957us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	36.670s	4.053ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.169m	11.470ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.970s	225.772us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	21.820s	6.941ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	21.820s	6.941ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	21.820s	6.941ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	36.670s	4.053ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.630s	174.957us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	21.820s	6.941ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.181m	3.973ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	36.670s	4.053ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	50.410s	3.314ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.27884234179914681819857626888043353676355322228076022803834811923872617738169
      Line 182, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3314173190 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3314173190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---