ROM_CTRL/32KB Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.210s	182.156us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	4.900s	637.490us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.410s	603.385us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.640s	373.030us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.970s	168.455us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.010s	409.017us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.410s	603.385us	1	1	100.00
		rom_ctrl_csr_aliasing	4.970s	168.455us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.650s	555.493us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.020s	171.297us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.950s	178.664us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	14.890s	1.808ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	6.020s	741.695us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.040s	298.481us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	6.340s	601.100us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	6.340s	601.100us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	4.900s	637.490us	1	1	100.00
		rom_ctrl_csr_rw	4.410s	603.385us	1	1	100.00
		rom_ctrl_csr_aliasing	4.970s	168.455us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.000s	297.880us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	4.900s	637.490us	1	1	100.00
		rom_ctrl_csr_rw	4.410s	603.385us	1	1	100.00
		rom_ctrl_csr_aliasing	4.970s	168.455us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.000s	297.880us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.303m	8.208ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	14.360s	1.525ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.726m	358.813us	0	1	0.00
		rom_ctrl_tl_intg_err	24.370s	909.327us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.726m	358.813us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.726m	358.813us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.303m	8.208ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.303m	8.208ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.303m	8.208ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.303m	8.208ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.303m	8.208ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.726m	358.813us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.726m	358.813us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.210s	182.156us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.210s	182.156us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.210s	182.156us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	24.370s	909.327us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.303m	8.208ms	1	1	100.00
		rom_ctrl_kmac_err_chk	6.020s	741.695us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.303m	8.208ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.303m	8.208ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.303m	8.208ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	14.360s	1.525ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.726m	358.813us	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	53.800s	2.141ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.67628128600856960549982382735306598440071107515989411204885441276973702750680
      Line 162, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 4340492ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 4340492ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 4340492ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))