ROM_CTRL/64KB Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.540s	307.890us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.190s	395.219us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.570s	1.028ms	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.340s	699.861us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.940s	376.675us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.690s	1.058ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.570s	1.028ms	1	1	100.00
		rom_ctrl_csr_aliasing	6.940s	376.675us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.550s	432.911us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.680s	222.974us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.840s	3.687ms	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	25.290s	2.762ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	12.350s	1.370ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	9.550s	291.046us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	7.400s	377.132us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	7.400s	377.132us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.190s	395.219us	1	1	100.00
		rom_ctrl_csr_rw	6.570s	1.028ms	1	1	100.00
		rom_ctrl_csr_aliasing	6.940s	376.675us	1	1	100.00
		rom_ctrl_same_csr_outstanding	8.090s	287.793us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.190s	395.219us	1	1	100.00
		rom_ctrl_csr_rw	6.570s	1.028ms	1	1	100.00
		rom_ctrl_csr_aliasing	6.940s	376.675us	1	1	100.00
		rom_ctrl_same_csr_outstanding	8.090s	287.793us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.892m	4.204ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	23.320s	737.378us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.985m	869.943us	0	1	0.00
		rom_ctrl_tl_intg_err	54.620s	2.913ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.985m	869.943us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.985m	869.943us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.892m	4.204ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.892m	4.204ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.892m	4.204ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.892m	4.204ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.892m	4.204ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.985m	869.943us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.985m	869.943us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.540s	307.890us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.540s	307.890us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.540s	307.890us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	54.620s	2.913ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.892m	4.204ms	1	1	100.00
		rom_ctrl_kmac_err_chk	12.350s	1.370ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.892m	4.204ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.892m	4.204ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.892m	4.204ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	23.320s	737.378us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.985m	869.943us	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.577m	3.504ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.7912141666032059820557948187706372415111443821605858195628370746458814542577
      Line 114, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 6837364ps failed at 6837364ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 6857772ps failed at 6857772ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'