RV_TIMER Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.990s	339.631us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.740s	14.021us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.590s	39.549us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.910s	988.466us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.950s	67.163us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.080s	24.381us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.590s	39.549us	1	1	100.00
		rv_timer_csr_aliasing	0.950s	67.163us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.780s	237.592us	0	1	0.00
V2	disabled	rv_timer_disabled	1.110s	1.436ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	11.498m	560.510ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	11.498m	560.510ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.610s	2.284ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.630s	27.059us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.710s	21.972us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.560s	713.868us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.560s	713.868us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.740s	14.021us	1	1	100.00
		rv_timer_csr_rw	0.590s	39.549us	1	1	100.00
		rv_timer_csr_aliasing	0.950s	67.163us	1	1	100.00
		rv_timer_same_csr_outstanding	0.630s	34.627us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.740s	14.021us	1	1	100.00
		rv_timer_csr_rw	0.590s	39.549us	1	1	100.00
		rv_timer_csr_aliasing	0.950s	67.163us	1	1	100.00
		rv_timer_same_csr_outstanding	0.630s	34.627us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.950s	259.851us	1	1	100.00
		rv_timer_tl_intg_err	1.290s	111.825us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.290s	111.825us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.770s	122.685us	0	1	0.00
V3	max_value	rv_timer_max	0.680s	86.251us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	41.820s	7.746ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.12879587868200796359584925147503925748657692369274921372596895237064521339808
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 122684526 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xff15bb04) == 0x1
        UVM_INFO @ 122684526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.26338181069455189119602073093808571824921832152887892529173396319397635196748
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 237592451 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3b2b5504) == 0x1
        UVM_INFO @ 237592451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.72450207136316037698663910982743156204302098163864804680920293242442420483643
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  86250729 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  86250729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---