SPI_DEVICE/1R1W Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.248m	9.194ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.470s	55.665us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.880s	63.274us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.620s	1.664ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.540s	202.391us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.990s	166.182us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.880s	63.274us	1	1	100.00
		spi_device_csr_aliasing	5.540s	202.391us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.860s	19.891us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.770s	77.902us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.780s	15.509us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.680s	12.586us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.760s	3.621us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.170s	120.704us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.170s	120.704us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.240s	504.613us	1	1	100.00
		spi_device_tpm_sts_read	0.980s	225.970us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.410s	8.902ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.450s	339.888us	1	1	100.00
		spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.500s	149.800us	1	1	100.00
		spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.500s	149.800us	1	1	100.00
		spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	19.030s	2.451ms	1	1	100.00
		spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	19.030s	2.451ms	1	1	100.00
		spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	19.030s	2.451ms	1	1	100.00
		spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	19.030s	2.451ms	1	1	100.00
		spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	19.030s	2.451ms	1	1	100.00
		spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.200s	268.054us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.020s	521.703us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.020s	521.703us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.020s	521.703us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	22.830s	2.674ms	1	1	100.00
		spi_device_read_buffer_direct	6.050s	608.260us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.020s	521.703us	1	1	100.00
		spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	41.780s	3.371ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	7.340s	16.255ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	7.340s	16.255ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.248m	9.194ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	41.340s	7.032ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.040s	76.414us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.920s	48.114us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.910s	19.913us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.830s	566.065us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.830s	566.065us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.470s	55.665us	1	1	100.00
		spi_device_csr_rw	1.880s	63.274us	1	1	100.00
		spi_device_csr_aliasing	5.540s	202.391us	1	1	100.00
		spi_device_same_csr_outstanding	2.120s	86.764us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.470s	55.665us	1	1	100.00
		spi_device_csr_rw	1.880s	63.274us	1	1	100.00
		spi_device_csr_aliasing	5.540s	202.391us	1	1	100.00
		spi_device_same_csr_outstanding	2.120s	86.764us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.220s	37.682us	1	1	100.00
		spi_device_tl_intg_err	11.740s	2.731ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.740s	2.731ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.320m	19.218ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.13527046585711689084132776289946016008293370349758056749432135816742379472381
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  10586144 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[45])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  10586144 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  10586144 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[941])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.86110414401789639636861127943114951693405773425803725137019727976699715142434
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1001648 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x55ff2c [10101011111111100101100] vs 0x0 [0])
        UVM_ERROR @   1066648 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9aaf99 [100110101010111110011001] vs 0x0 [0])
        UVM_ERROR @   1087648 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1d3ce8 [111010011110011101000] vs 0x0 [0])
        UVM_ERROR @   1151648 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x77c2b4 [11101111100001010110100] vs 0x0 [0])
        UVM_ERROR @   1248648 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1d700b [111010111000000001011] vs 0x0 [0])