| V1 |
smoke |
spi_host_smoke |
32.000s |
3.845ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_host_csr_hw_reset |
1.000s |
50.034us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_host_csr_rw |
1.000s |
48.824us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_host_csr_bit_bash |
2.000s |
38.306us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_host_csr_aliasing |
1.000s |
85.633us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_host_csr_mem_rw_with_rand_reset |
1.000s |
22.424us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_host_csr_rw |
1.000s |
48.824us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
1.000s |
85.633us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_host_mem_walk |
2.000s |
16.270us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_host_mem_partial_access |
1.000s |
53.195us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
performance |
spi_host_performance |
9.000s |
67.898us |
1 |
1 |
100.00 |
| V2 |
error_event_intr |
spi_host_overflow_underflow |
6.000s |
724.981us |
1 |
1 |
100.00 |
|
|
spi_host_error_cmd |
2.000s |
32.173us |
1 |
1 |
100.00 |
|
|
spi_host_event |
10.000s |
955.285us |
1 |
1 |
100.00 |
| V2 |
clock_rate |
spi_host_speed |
11.000s |
127.330us |
1 |
1 |
100.00 |
| V2 |
speed |
spi_host_speed |
11.000s |
127.330us |
1 |
1 |
100.00 |
| V2 |
chip_select_timing |
spi_host_speed |
11.000s |
127.330us |
1 |
1 |
100.00 |
| V2 |
sw_reset |
spi_host_sw_reset |
3.000s |
95.551us |
1 |
1 |
100.00 |
| V2 |
passthrough_mode |
spi_host_passthrough_mode |
1.000s |
35.792us |
1 |
1 |
100.00 |
| V2 |
cpol_cpha |
spi_host_speed |
11.000s |
127.330us |
1 |
1 |
100.00 |
| V2 |
full_cycle |
spi_host_speed |
11.000s |
127.330us |
1 |
1 |
100.00 |
| V2 |
duplex |
spi_host_smoke |
32.000s |
3.845ms |
1 |
1 |
100.00 |
| V2 |
tx_rx_only |
spi_host_smoke |
32.000s |
3.845ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_host_stress_all |
8.000s |
686.907us |
1 |
1 |
100.00 |
| V2 |
spien |
spi_host_spien |
3.000s |
430.032us |
1 |
1 |
100.00 |
| V2 |
stall |
spi_host_status_stall |
16.000s |
909.129us |
1 |
1 |
100.00 |
| V2 |
Idlecsbactive |
spi_host_idlecsbactive |
2.000s |
257.860us |
1 |
1 |
100.00 |
| V2 |
data_fifo_status |
spi_host_overflow_underflow |
6.000s |
724.981us |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_host_alert_test |
1.000s |
18.535us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_host_intr_test |
2.000s |
34.149us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_host_tl_errors |
2.000s |
61.544us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_host_tl_errors |
2.000s |
61.544us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_host_csr_hw_reset |
1.000s |
50.034us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
1.000s |
48.824us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
1.000s |
85.633us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
1.000s |
29.949us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_host_csr_hw_reset |
1.000s |
50.034us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
1.000s |
48.824us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
1.000s |
85.633us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
1.000s |
29.949us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
15 |
15 |
100.00 |
| V2S |
tl_intg_err |
spi_host_tl_intg_err |
2.000s |
161.247us |
1 |
1 |
100.00 |
|
|
spi_host_sec_cm |
1.000s |
340.601us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_host_tl_intg_err |
2.000s |
161.247us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_host_upper_range_clkdiv |
2.250m |
10.688ms |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
26 |
26 |
100.00 |