SRAM_CTRL/MAIN Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	23.930s	760.377us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.790s	16.823us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.810s	15.388us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.500s	43.360us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	36.129us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.890s	1.253ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.810s	15.388us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	36.129us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.125m	8.042ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.029m	2.533ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	12.244m	42.825ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.193m	4.944ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	29.645m	222.648ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.295m	13.466ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	38.190s	9.343ms	1	1	100.00
V2	executable	sram_ctrl_executable	2.698m	5.385ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	15.150s	669.889us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.963m	97.455ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	16.200s	753.884us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	31.890s	3.594ms	1	1	100.00
		sram_ctrl_throughput_w_readback	21.470s	819.861us	1	1	100.00
V2	regwen	sram_ctrl_regwen	36.000s	1.746ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.550s	1.411ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	52.016m	197.241ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.810s	11.927us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.880s	719.692us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.880s	719.692us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.790s	16.823us	1	1	100.00
		sram_ctrl_csr_rw	0.810s	15.388us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	36.129us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.840s	160.992us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.790s	16.823us	1	1	100.00
		sram_ctrl_csr_rw	0.810s	15.388us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	36.129us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.840s	160.992us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	33.180s	7.118ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.110s	7.657us	0	1	0.00
		sram_ctrl_tl_intg_err	1.500s	117.100us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.110s	7.657us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.500s	117.100us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	36.000s	1.746ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	36.000s	1.746ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.810s	15.388us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.698m	5.385ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.698m	5.385ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.698m	5.385ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	38.190s	9.343ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.870s	1.388ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	33.180s	7.118ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.580s	2.669ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	23.930s	760.377us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	23.930s	760.377us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.698m	5.385ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.110s	7.657us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	38.190s	9.343ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.110s	7.657us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.110s	7.657us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	23.930s	760.377us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.110s	7.657us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	23.310s	4.912ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.36736272478812260265511127863825753020424830161568932216335319974023592009954
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7656545 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7656545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---