UART Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: dbeac2b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	7.680s	5.385ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.750s	28.057us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.840s	16.128us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.480s	129.754us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	22.840us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.100s	161.145us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.840s	16.128us	1	1	100.00
		uart_csr_aliasing	0.750s	22.840us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	38.780s	77.839ms	1	1	100.00
V2	parity	uart_smoke	7.680s	5.385ms	1	1	100.00
		uart_tx_rx	38.780s	77.839ms	1	1	100.00
V2	parity_error	uart_intr	4.815m	232.492ms	1	1	100.00
		uart_rx_parity_err	3.053m	135.647ms	1	1	100.00
V2	watermark	uart_tx_rx	38.780s	77.839ms	1	1	100.00
		uart_intr	4.815m	232.492ms	1	1	100.00
V2	fifo_full	uart_fifo_full	12.860s	21.571ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	12.090s	9.528ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	39.840s	28.189ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.815m	232.492ms	1	1	100.00
V2	rx_break_err	uart_intr	4.815m	232.492ms	1	1	100.00
V2	rx_timeout	uart_intr	4.815m	232.492ms	1	1	100.00
V2	perf	uart_perf	15.649m	29.548ms	1	1	100.00
V2	sys_loopback	uart_loopback	0.960s	193.238us	1	1	100.00
V2	line_loopback	uart_loopback	0.960s	193.238us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.320s	275.648us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.740s	2.935ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.480s	4.537ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	23.930s	3.799ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.244m	77.786ms	1	1	100.00
V2	stress_all	uart_stress_all	1.920s	3.343ms	0	1	0.00
V2	alert_test	uart_alert_test	0.670s	44.806us	1	1	100.00
V2	intr_test	uart_intr_test	0.670s	38.721us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.200s	94.701us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.200s	94.701us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.750s	28.057us	1	1	100.00
		uart_csr_rw	0.840s	16.128us	1	1	100.00
		uart_csr_aliasing	0.750s	22.840us	1	1	100.00
		uart_same_csr_outstanding	0.990s	16.623us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.750s	28.057us	1	1	100.00
		uart_csr_rw	0.840s	16.128us	1	1	100.00
		uart_csr_aliasing	0.750s	22.840us	1	1	100.00
		uart_same_csr_outstanding	0.990s	16.623us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.100s	75.743us	1	1	100.00
		uart_tl_intg_err	1.420s	78.886us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.420s	78.886us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	47.000s	1.692ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.8919543347288993327913927248164401106789361665958027779120321156721842296452
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @  81343563 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
        UVM_ERROR @  81353872 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @  81364181 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @  81374490 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @  81384799 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.9128260217080686037155060228545439890304251071400922792988389337976789754948
      Line 75, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 907404782 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 907404782 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 995205221 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 999938578 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
        UVM_ERROR @ 1339606943 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 255 [0xff]) reg name: uart_reg_block.rdata