CHIP Simulation Results

Thursday October 02 2025 16:01:20 UTC

GitHub Revision: `dbeac2b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.122m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.122m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	43.544s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	34.432s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.330s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.847m	5.041ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.847m	5.041ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.847m	5.041ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	32.110s	10.280us	0	1	0.00
		chip_sw_example_manufacturer	2.363m		0	1	0.00
		chip_sw_example_concurrency	4.449m	3.548ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.994s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	11.600s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	14.300s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	14.300s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.380s	12.128us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.252m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.196m	8.593ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.802m	5.217ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	13.506s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	17.323s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	18.650s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.843s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.000s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.000s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.324m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.263m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.673m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.673m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.067m	4.449ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.048m	5.416ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.885m	15.089ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.156s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.079s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.803m	12.145ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.615m	5.725ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.863m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.863m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.353s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.799m	3.592ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.799m	3.592ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.875m	18.027ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.800m	3.236ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.454m	6.318ms	1	1	100.00
		chip_sw_aes_idle	3.720m	3.381ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.224m	5.101ms	1	1	100.00
		chip_sw_kmac_idle	4.472m	4.280ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.343m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.437m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	16.678m	11.891ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	11.987m	12.027ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.662s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.377s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.744s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.239s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.187s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.047s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.554s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.662s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.377s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.744s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.239s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.187s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.047s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.554s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.509s		0	1	0.00
		chip_sw_aes_enc_jitter_en	37.170s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	50.360s	10.160us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	39.460s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.980s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.367s		0	1	0.00
		chip_sw_clkmgr_jitter	4.822m	4.724ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.287m	4.756ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.864s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	36.850s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	43.980s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	37.800s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	41.090s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	37.570s	10.300us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.894s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.746s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.927s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.816s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	21.508m	13.966ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.263m	13.590ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.799m	3.592ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.076s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.263m	13.590ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	11.918s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	14.268s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.218s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.143s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.753s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	21.508m	13.966ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.885m	15.089ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	25.241m	20.019ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.430m	7.854ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.595m	8.889ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.258m	4.971ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	21.508m	13.966ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.464s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.102s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	21.508m	13.966ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	13.140s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.595m	8.889ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	15.478s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.541s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.026s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.244s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.097s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.225s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.102s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.056s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.026s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.056s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.056s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.056s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.502m	7.837ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.242s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.719s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	20.208s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.135s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.056s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.538m	9.871ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.690m	13.729ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.400s		0	1	0.00
		chip_prim_tl_access	7.915m	12.287ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.662s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.377s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.744s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.239s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	15.187s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.047s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.554s		0	1	0.00
		chip_rv_dm_lc_disabled	12.803m	12.145ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.732m	3.944ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	37.170s	10.360us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.706m	3.570ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.720m	3.381ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.182m	4.114ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	50.360s	10.160us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.224m	5.101ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.729m	4.427ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.689m	5.558ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	39.980s	10.300us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.538m	9.871ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.056s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	32.170s	10.280us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.494m	6.156ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.472m	4.280ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.437s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.437s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	15.826s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.354m	3.901ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.828s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.538m	9.871ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	39.460s	10.200us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.277s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.509s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.454m	6.318ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.454m	6.318ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.454m	6.318ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.695m	6.165ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.690m	13.729ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.690m	13.729ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.489m	9.639ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.367s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.400s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	21.508m	13.966ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.673m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.056s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.695m	6.165ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.538m	9.871ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.489m	9.639ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.692m	4.905ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.695m	6.165ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.538m	9.871ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.489m	9.639ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.692m	4.905ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.056s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.331s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.026s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.242s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.719s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	20.208s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.135s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.056s		0	1	0.00
		chip_prim_tl_access	7.915m	12.287ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.915m	12.287ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.414s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.564s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.746s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.509s		0	1	0.00
		chip_sw_aes_enc_jitter_en	37.170s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	50.360s	10.160us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	39.460s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.980s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.367s		0	1	0.00
		chip_sw_clkmgr_jitter	4.822m	4.724ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.461m	6.282ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.461m	6.282ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.799m	5.962ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.950m	3.626ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.966m	4.521ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.956m	5.350ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.495m	6.199ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.695m	3.590ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.692m	4.905ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	25.241m	20.019ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	25.241m	20.019ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.993m	4.132ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.080m	3.748ms	1	1	100.00
		chip_sw_clkmgr_smoketest	4.387m	5.819ms	1	1	100.00
		chip_sw_csrng_smoketest	3.465m	3.518ms	1	1	100.00
		chip_sw_gpio_smoketest	3.288m	4.102ms	1	1	100.00
		chip_sw_hmac_smoketest	4.813m	4.777ms	1	1	100.00
		chip_sw_kmac_smoketest	4.365m	4.524ms	1	1	100.00
		chip_sw_otbn_smoketest	4.838m	5.783ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.537m	3.591ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.635m	4.644ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.189m	5.856ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.157m	3.328ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.250m	3.615ms	1	1	100.00
		chip_sw_uart_smoketest	3.539m	4.640ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.791s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.994s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.252m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.854s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.426m	6.236ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.761m	3.680ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.946m	3.543ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	40.114m	60.000ms	0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	17.181s		0	1	0.00
		chip_rv_dm_lc_disabled	12.803m	12.145ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.768s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.873s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.659s		0	1	0.00
		chip_sw_lc_walkthrough_rma	17.715s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	17.181s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.364s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.028s		0	1	0.00
		rom_volatile_raw_unlock	12.740s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	12.215s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.015m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.114m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.857m	4.430ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.857m	4.430ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	14.300s		0	1	0.00
		chip_same_csr_outstanding	14.860s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	14.300s		0	1	0.00
		chip_same_csr_outstanding	14.860s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.298m	473.395us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.220s	13.290us	1	1	100.00
		xbar_smoke_large_delays	4.749m	2.490ms	1	1	100.00
		xbar_smoke_slow_rsp	5.770m	2.147ms	1	1	100.00
		xbar_random_zero_delays	1.114m	66.923us	1	1	100.00
		xbar_random_large_delays	19.562m	9.712ms	1	1	100.00
		xbar_random_slow_rsp	27.232m	9.790ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	52.380s	33.059us	1	1	100.00
		xbar_error_and_unmapped_addr	1.207m	43.406us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.615m	477.060us	1	1	100.00
		xbar_error_and_unmapped_addr	1.207m	43.406us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.983m	470.983us	1	1	100.00
		xbar_access_same_device_slow_rsp	6.739m	2.363ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.682m	478.735us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	7.327m	1.219ms	1	1	100.00
		xbar_stress_all_with_error	2.436m	126.563us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	28.272m	2.995ms	1	1	100.00
		xbar_stress_all_with_reset_error	17.703m	1.478ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.275s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.947s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.151s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.103s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.387s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	14.684s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.765s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	13.919s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.639s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.867s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.507s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	13.431s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.744s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	44.153s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	45.961s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	45.735s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	40.880s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	40.702s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	43.522s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	35.320s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	27.426s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	21.859s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	27.943s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	35.740s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	36.458s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	36.484s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	36.949s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	29.951s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.202s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.016s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.377s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.801s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.453s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	15.037s		0	1	0.00
		rom_e2e_asm_init_dev	12.161s		0	1	0.00
		rom_e2e_asm_init_prod	12.843s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.926s		0	1	0.00
		rom_e2e_asm_init_rma	11.405s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.530s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.114s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.317s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.417s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.480m	4.570ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.532m	3.200ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.732s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.732s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.398s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.682s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	21.508m	13.966ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	17.181s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	20.486m	11.967ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.887s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.589s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.732s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.732s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.398s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.344s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.727s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.154s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.477s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	22.277m	15.934ms	1	1	100.00
		chip_sw_entropy_src_kat_test	4.406m	4.542ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.971m	5.304ms	1	1	100.00
		chip_plic_all_irqs_0	10.741m	7.847ms	1	1	100.00
		chip_plic_all_irqs_10	10.961m	6.218ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.317m	3.833ms	1	1	100.00
		chip_sw_dma_abort	4.656m	3.845ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.158s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.734s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.099s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.512s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.231s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	12.330s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.402s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.994s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.511s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.297s		0	1	0.00
		chip_sw_entropy_src_smoketest	3.648m	3.503ms	1	1	100.00
		chip_sw_mbx_smoketest	4.409m	3.989ms	1	1	100.00
		TOTAL			77	250	30.80

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.106421352975607399177958534532402485849741881540492669344529227968889041526107
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 130.739s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.36062313568792377252189216691642320797246066765310323732616374648920230933551
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 89.654s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.76169877731437557694333535526897156454784198500633282885672875586678525637407
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 69.106s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.24397122709503082662672991877196904611349226687403242218321528077955958077739
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 61.049s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.81857710999352828354393789877996639987758137003396706338017927010442494348733
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 52.897s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.65297619432610420546549358593201048294303817421138793303479292313932119131077
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.9034817544215399203755292965078238783424206360697325830273691080829582947747
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.24115814273011528706137899212622686822460693428386557582885317533535531667194
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.16019808929909082997739396266731555818519681321091364764596336382952426053993
    Line 379, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.57032771495967971188466993129042089231564767061033913332812295400941685878783
    Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.106463305918096326167276192261814194727764495722117849835332720898443998426988
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.90843891637432488602731354192377200688788165723133870116381110669295445575964
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.9258814202176663327800425423307806860465519391533300215697937067559130182810
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.18687005098823325510730760882375386852767874550611281965456205307239721308406
Line 426, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.665507 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.665507 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.6376880991436127955960110343941180730973311443120504769049538646995416291579
Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.827584 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.827584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.107134942286491888839370614914064408921728250233502753682208065336017470922475
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18026.880416 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.880416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.87270810788522257865779080608943863003393790801918728250741351052444175427990
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.767216 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.767216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.32895738188769837667932192669503173641273266429928117182613987439425516944443
Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.612157 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.612157 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.92037614325915824859185478551683418456103249825671318777704976022009062681268
Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.956805 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.956805 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.58484053129242821595867926833661879134520345490200765258369265921029549486641
Line 409, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9871.299960 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11780874367012949863347143599519627703814223155525707445727212048814484401520263674556386981584087992708424963727776332338076864524325680773258514448866396 [0xe0efb6e2aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd366b906137f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 9871.299960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.70453299504774220631481803040420083493620934722812038528130826662454301375739
Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7837.027255 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (859315858723236473144250069194191433677765558340818764276548167937006958576203730987930122980755363181497647792288758970151798459538887212316485552004188 [0x10683f98aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3963e8f697f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 7837.027255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.76521446593228895264538999771526951261248027753693674696470412311031181951301
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4448.977572 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h5a4111b4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h0  a_user: 'h2695d  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4448.977572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.80689873976019653696435805004360587239551070874315204976428021698853031368697
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5415.573519 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h7e4c169  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h0  a_user: 'h26967  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5415.573519 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.17073081277562854219415574853918290904489801872776034446605407102976378057051
    Line 1365, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.102126443152109968112098603304660283899338785598153925860001510219159922137232
    Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5216.886662 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5216.886662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_rand_to_scrap.115762409577538471861833904166210983071079534736967852183768045097085422527062
    Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.946209854193952825566281514459140618016128913945839639025992005890182079093
    Line 641, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8888.685212 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8888.685212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.89833081444130400904850639932395500803413280955885096968775931093336799856596
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5962.466390 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5962.466390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.65197473720718096863899551693109571784950032652858609675847583653227135257920
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3625.774402 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3625.774402 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.26264792492570874722601480231733345942412547312232442803632088430122165476128
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3592.055282 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3592.055282 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.99967982231392313481109352276405590180155149187093935647220570429228041894834
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5349.796536 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5349.796536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.8836412756315169619118865751831322090320771979892727669614662295723543462986
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.34758263601307624468404688657613526679576056125032444825909144202828542367877
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4430.444248 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4430.444248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.12636743979097904812010427669383045695861523749103789788972582073958641255328
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15089.416480 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15089.416480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.28764022098633738803929374565265787529184882768791248699729001070699684446984
    Line 249, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 12145.269010 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40448 read out mismatch
  UVM_INFO @ 12145.269010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(outstanding_load_resp | outstanding_store_resp)' has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.79238569421980716935095911040507765060070379564752207045131245903225936711068
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
      Offending '(outstanding_load_resp | outstanding_store_resp)'
  UVM_ERROR @ 3200.310976 us: (ibex_core.sv:1003) [ASSERT FAILED] NoMemResponseWithoutPendingAccess
  UVM_INFO @ 3200.310976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.62138601221284352455563226346668846436838362084182114852437497411932982419239
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.101032637779263095460419716598484910132932686693088254864693246229275329782693
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3844.538424 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3844.538424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```