DMA Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	590.479us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	4.541ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	337.926us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	79.235us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	19.938us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	309.276us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	3.000s	281.850us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	50.256us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	19.938us	1	1	100.00
		dma_csr_aliasing	3.000s	281.850us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	55.000s	30.335ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	2.317m	28.986ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	2.900m	18.240ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	2.900m	18.240ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	2.317m	28.986ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	14.900m	91.682ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	2.900m	18.240ms	1	1	100.00
V2	dma_abort	dma_abort	9.000s	3.091ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	3.033m	31.952ms	1	1	100.00
V2	alert_test	dma_alert_test	1.000s	29.383us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	15.176us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	33.162us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	33.162us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	79.235us	1	1	100.00
		dma_csr_rw	1.000s	19.938us	1	1	100.00
		dma_csr_aliasing	3.000s	281.850us	1	1	100.00
		dma_same_csr_outstanding	2.000s	110.106us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	79.235us	1	1	100.00
		dma_csr_rw	1.000s	19.938us	1	1	100.00
		dma_csr_aliasing	3.000s	281.850us	1	1	100.00
		dma_same_csr_outstanding	2.000s	110.106us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	9.000s	192.447us	1	1	100.00
		dma_generic_stress	14.900m	91.682ms	1	1	100.00
		dma_handshake_stress	2.900m	18.240ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	9.000s	2.603ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	324.883us	1	1	100.00
		dma_sec_cm	2.000s	13.286us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	47.000s	17.939ms	1	1	100.00
		dma_longer_transfer	4.000s	115.645us	1	1	100.00
		dma_stress_all_with_rand_reset	6.000s	176.741us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.30389891634150195377746182085275183184499207528915474084780604224195179311917
      Line 95, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  176741016ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  176741016ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---