EDN Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.950s	20.621us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.060s	73.958us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.800s	19.284us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.810s	451.774us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.980s	34.331us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.270s	343.718us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.800s	19.284us	1	1	100.00
		edn_csr_aliasing	0.980s	34.331us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.250s	142.200us	1	1	100.00
V2	csrng_commands	edn_genbits	2.250s	142.200us	1	1	100.00
V2	genbits	edn_genbits	2.250s	142.200us	1	1	100.00
V2	interrupts	edn_intr	0.780s	22.354us	1	1	100.00
V2	alerts	edn_alert	1.040s	99.514us	1	1	100.00
V2	errs	edn_err	0.720s	27.039us	1	1	100.00
V2	disable	edn_disable	0.760s	36.446us	1	1	100.00
		edn_disable_auto_req_mode	1.200s	46.772us	1	1	100.00
V2	stress_all	edn_stress_all	2.120s	258.738us	1	1	100.00
V2	intr_test	edn_intr_test	0.810s	36.864us	1	1	100.00
V2	alert_test	edn_alert_test	0.850s	97.113us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.430s	823.427us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.430s	823.427us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.060s	73.958us	1	1	100.00
		edn_csr_rw	0.800s	19.284us	1	1	100.00
		edn_csr_aliasing	0.980s	34.331us	1	1	100.00
		edn_same_csr_outstanding	0.950s	27.661us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.060s	73.958us	1	1	100.00
		edn_csr_rw	0.800s	19.284us	1	1	100.00
		edn_csr_aliasing	0.980s	34.331us	1	1	100.00
		edn_same_csr_outstanding	0.950s	27.661us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.750s	1.034ms	1	1	100.00
		edn_tl_intg_err	2.050s	100.319us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.860s	43.730us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.040s	99.514us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.750s	1.034ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.750s	1.034ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.750s	1.034ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.750s	1.034ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.040s	99.514us	1	1	100.00
		edn_sec_cm	3.750s	1.034ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.040s	99.514us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.050s	100.319us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.689m	5.320ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00