HMAC Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.040s 130.607us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.730s 22.010us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.650s 40.549us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.650s 762.900us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.500s 381.274us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.120s 114.733us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.650s 40.549us 1 1 100.00
hmac_csr_aliasing 4.500s 381.274us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 20.160s 27.501ms 1 1 100.00
V2 back_pressure hmac_back_pressure 10.800s 1.259ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.934m 7.575ms 1 1 100.00
hmac_test_sha384_vectors 5.865m 64.947ms 1 1 100.00
hmac_test_sha512_vectors 5.395m 17.398ms 1 1 100.00
hmac_test_hmac256_vectors 9.270s 438.022us 1 1 100.00
hmac_test_hmac384_vectors 9.330s 1.368ms 1 1 100.00
hmac_test_hmac512_vectors 9.350s 280.395us 1 1 100.00
V2 burst_wr hmac_burst_wr 15.020s 1.610ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 16.023m 24.910ms 1 1 100.00
V2 error hmac_error 3.400s 419.193us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 17.680s 3.955ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.040s 130.607us 1 1 100.00
hmac_long_msg 20.160s 27.501ms 1 1 100.00
hmac_back_pressure 10.800s 1.259ms 1 1 100.00
hmac_datapath_stress 16.023m 24.910ms 1 1 100.00
hmac_burst_wr 15.020s 1.610ms 1 1 100.00
hmac_stress_all 20.276m 110.279ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.040s 130.607us 1 1 100.00
hmac_long_msg 20.160s 27.501ms 1 1 100.00
hmac_back_pressure 10.800s 1.259ms 1 1 100.00
hmac_datapath_stress 16.023m 24.910ms 1 1 100.00
hmac_wipe_secret 17.680s 3.955ms 1 1 100.00
hmac_test_sha256_vectors 3.934m 7.575ms 1 1 100.00
hmac_test_sha384_vectors 5.865m 64.947ms 1 1 100.00
hmac_test_sha512_vectors 5.395m 17.398ms 1 1 100.00
hmac_test_hmac256_vectors 9.270s 438.022us 1 1 100.00
hmac_test_hmac384_vectors 9.330s 1.368ms 1 1 100.00
hmac_test_hmac512_vectors 9.350s 280.395us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.040s 130.607us 1 1 100.00
hmac_long_msg 20.160s 27.501ms 1 1 100.00
hmac_back_pressure 10.800s 1.259ms 1 1 100.00
hmac_datapath_stress 16.023m 24.910ms 1 1 100.00
hmac_burst_wr 15.020s 1.610ms 1 1 100.00
hmac_error 3.400s 419.193us 1 1 100.00
hmac_wipe_secret 17.680s 3.955ms 1 1 100.00
hmac_test_sha256_vectors 3.934m 7.575ms 1 1 100.00
hmac_test_sha384_vectors 5.865m 64.947ms 1 1 100.00
hmac_test_sha512_vectors 5.395m 17.398ms 1 1 100.00
hmac_test_hmac256_vectors 9.270s 438.022us 1 1 100.00
hmac_test_hmac384_vectors 9.330s 1.368ms 1 1 100.00
hmac_test_hmac512_vectors 9.350s 280.395us 1 1 100.00
hmac_stress_all 20.276m 110.279ms 1 1 100.00
V2 stress_all hmac_stress_all 20.276m 110.279ms 1 1 100.00
V2 alert_test hmac_alert_test 0.580s 14.684us 1 1 100.00
V2 intr_test hmac_intr_test 0.680s 16.209us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.440s 35.708us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.440s 35.708us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.730s 22.010us 1 1 100.00
hmac_csr_rw 0.650s 40.549us 1 1 100.00
hmac_csr_aliasing 4.500s 381.274us 1 1 100.00
hmac_same_csr_outstanding 1.350s 36.930us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.730s 22.010us 1 1 100.00
hmac_csr_rw 0.650s 40.549us 1 1 100.00
hmac_csr_aliasing 4.500s 381.274us 1 1 100.00
hmac_same_csr_outstanding 1.350s 36.930us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.720s 255.106us 1 1 100.00
hmac_tl_intg_err 3.280s 235.412us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.280s 235.412us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.040s 130.607us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.010s 549.994us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.272m 5.276ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.570s 681.039us 1 1 100.00
TOTAL 28 28 100.00