I2C Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	34.500s	39.154ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.000s	644.563us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.750s	19.085us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.080s	81.113us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.910s	849.531us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.450s	61.647us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.070s	98.874us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.080s	81.113us	1	1	100.00
		i2c_csr_aliasing	1.450s	61.647us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.570s	137.128us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	17.398m	17.641ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.014m	25.973ms	1	1	100.00
V2	host_override	i2c_host_override	0.770s	325.262us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.237m	4.170ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	52.570s	16.035ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.130s	192.164us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.130s	399.647us	1	1	100.00
		i2c_host_fifo_reset_rx	3.920s	289.343us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.954m	12.398ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	11.350s	765.678us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.440s	238.965us	1	1	100.00
V2	target_glitch	i2c_target_glitch	3.160s	1.839ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.062m	22.844ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.740s	534.024us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	13.450s	3.955ms	1	1	100.00
		i2c_target_intr_smoke	3.870s	775.554us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.030s	115.452us	1	1	100.00
		i2c_target_fifo_reset_tx	1.330s	221.147us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	7.360s	22.539ms	1	1	100.00
		i2c_target_stress_rd	13.450s	3.955ms	1	1	100.00
		i2c_target_intr_stress_wr	58.340s	12.985ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.190s	3.121ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.810s	2.363ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.380s	931.988us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.680s	212.320us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.370s	919.616us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.330s	345.656us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.014m	25.973ms	1	1	100.00
		i2c_host_perf_precise	1.170s	72.604us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	11.350s	765.678us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.180s	204.086us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.190s	527.953us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.790s	529.771us	1	1	100.00
		i2c_target_nack_txstretch	1.420s	148.625us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.980s	1.443ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.470s	1.507ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.600s	19.056us	1	1	100.00
V2	intr_test	i2c_intr_test	0.780s	42.771us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.810s	78.919us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.810s	78.919us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.750s	19.085us	1	1	100.00
		i2c_csr_rw	1.080s	81.113us	1	1	100.00
		i2c_csr_aliasing	1.450s	61.647us	1	1	100.00
		i2c_same_csr_outstanding	1.180s	87.282us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.750s	19.085us	1	1	100.00
		i2c_csr_rw	1.080s	81.113us	1	1	100.00
		i2c_csr_aliasing	1.450s	61.647us	1	1	100.00
		i2c_same_csr_outstanding	1.180s	87.282us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	1.560s	170.005us	1	1	100.00
		i2c_sec_cm	0.880s	70.886us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.560s	170.005us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	2.700s	421.166us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.110s	62.615us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	2.870s	175.438us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.61882920124711356145240682438912730221066887282969672553071531821452763840211
      Line 107, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 137127828 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 137127828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.34851674435381222879285840249712550992573381028258133096089237397575820217240
      Line 162, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 17640910287 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 17640910287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.51294240226822932081574049469355721957270982235133864973878636926303503281862
      Line 95, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 175437611 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 175437611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.65744798476547897517180331288166965181716301892398601083231682052471896811083
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1838741156 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1838741156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.6807591389627090751264757816130389289993741311583902681336944584689166715618
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  62615003 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 200 [0xc8])
        UVM_INFO @  62615003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.73772318962081300756003596047458916063507329869897444095992735887230386011445
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 421166251 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 421166251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---