KEYMGR Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 2.150s 75.685us 1 1 100.00
V1 random keymgr_random 7.860s 341.448us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.790s 19.424us 1 1 100.00
V1 csr_rw keymgr_csr_rw 0.840s 42.490us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 10.560s 2.344ms 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 2.750s 65.729us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.040s 24.295us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.840s 42.490us 1 1 100.00
keymgr_csr_aliasing 2.750s 65.729us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 6.660s 723.289us 1 1 100.00
V2 sideload keymgr_sideload 2.280s 297.699us 1 1 100.00
keymgr_sideload_kmac 2.310s 78.658us 1 1 100.00
keymgr_sideload_aes 2.670s 74.401us 1 1 100.00
keymgr_sideload_otbn 2.230s 60.153us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 15.030s 704.792us 1 1 100.00
V2 lc_disable keymgr_lc_disable 3.830s 285.069us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 3.020s 377.562us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 4.220s 324.121us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.790s 30.495us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 2.490s 403.822us 1 1 100.00
V2 stress_all keymgr_stress_all 30.350s 2.148ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.690s 8.364us 1 1 100.00
V2 alert_test keymgr_alert_test 0.990s 17.135us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 1.880s 118.877us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 1.880s 118.877us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.790s 19.424us 1 1 100.00
keymgr_csr_rw 0.840s 42.490us 1 1 100.00
keymgr_csr_aliasing 2.750s 65.729us 1 1 100.00
keymgr_same_csr_outstanding 1.270s 44.919us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.790s 19.424us 1 1 100.00
keymgr_csr_rw 0.840s 42.490us 1 1 100.00
keymgr_csr_aliasing 2.750s 65.729us 1 1 100.00
keymgr_same_csr_outstanding 1.270s 44.919us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 5.700s 464.224us 1 1 100.00
keymgr_tl_intg_err 3.400s 913.978us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 2.120s 287.989us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 2.120s 287.989us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 2.120s 287.989us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 2.120s 287.989us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 5.410s 2.759ms 1 1 100.00
V2S prim_count_check keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 3.400s 913.978us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 2.120s 287.989us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 6.660s 723.289us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 7.860s 341.448us 1 1 100.00
keymgr_csr_rw 0.840s 42.490us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 7.860s 341.448us 1 1 100.00
keymgr_csr_rw 0.840s 42.490us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 7.860s 341.448us 1 1 100.00
keymgr_csr_rw 0.840s 42.490us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 3.830s 285.069us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.790s 30.495us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.790s 30.495us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 7.860s 341.448us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 1.790s 53.095us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 3.800s 176.678us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 3.830s 285.069us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 3.800s 176.678us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 3.800s 176.678us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 3.800s 176.678us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 5.700s 464.224us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 3.800s 176.678us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 7.580s 552.611us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00