| V1 |
smoke |
keymgr_dpe_smoke |
2.826m |
19.234ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
0.920s |
64.820us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
0.950s |
23.260us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
3.740s |
184.269us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
1.930s |
45.974us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
0.970s |
114.184us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
0.950s |
23.260us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
1.930s |
45.974us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.830s |
7.197us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.720s |
20.866us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.030s |
164.893us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.030s |
164.893us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
0.920s |
64.820us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.950s |
23.260us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
1.930s |
45.974us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.150s |
75.289us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
0.920s |
64.820us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.950s |
23.260us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
1.930s |
45.974us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.150s |
75.289us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
4.750s |
1.966ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
2.130s |
185.435us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.850s |
131.484us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.850s |
131.484us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.850s |
131.484us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.850s |
131.484us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
2.800s |
303.174us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
4.750s |
1.966ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
4.750s |
1.966ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |