| V1 |
smoke |
kmac_smoke |
7.980s |
523.266us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.100s |
41.391us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
0.970s |
20.689us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
6.550s |
515.460us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
3.550s |
445.462us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
2.000s |
517.164us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
0.970s |
20.689us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.550s |
445.462us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.830s |
68.161us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.230s |
38.915us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
1.950m |
7.219ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
9.411m |
29.073ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
24.803m |
20.455ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
22.548m |
37.955ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
23.620s |
2.117ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
17.626m |
84.090ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
33.855m |
73.717ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
24.089m |
17.540ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.470s |
57.939us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.730s |
32.528us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
2.967m |
8.339ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
2.722m |
4.237ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
4.291m |
64.148ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
5.590m |
211.742ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
4.712m |
15.172ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
6.720s |
5.090ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
3.590s |
2.315ms |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
0.800s |
55.227us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.080s |
81.612us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
43.810s |
5.890ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.430s |
40.750us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
22.056m |
86.224ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
0.740s |
144.286us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.080s |
44.470us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
1.740s |
67.800us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
1.740s |
67.800us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.100s |
41.391us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.970s |
20.689us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.550s |
445.462us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.540s |
94.852us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.100s |
41.391us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
0.970s |
20.689us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.550s |
445.462us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
1.540s |
94.852us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.230s |
123.682us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.230s |
123.682us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.230s |
123.682us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.230s |
123.682us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
2.090s |
52.981us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
47.330s |
4.850ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
1.840s |
565.288us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
1.840s |
565.288us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.430s |
40.750us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
7.980s |
523.266us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
2.967m |
8.339ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.230s |
123.682us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
47.330s |
4.850ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
47.330s |
4.850ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
47.330s |
4.850ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
7.980s |
523.266us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.430s |
40.750us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
47.330s |
4.850ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
11.120s |
992.320us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
7.980s |
523.266us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.816m |
12.781ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |