MBX Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	16.000s	833.195us	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	10.000s	22.716us	1	1	100.00
V1	csr_rw	mbx_csr_rw	8.000s	160.539us	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	9.000s	136.442us	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	7.000s	28.812us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	1.000s	33.423us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	8.000s	160.539us	1	1	100.00
		mbx_csr_aliasing	7.000s	28.812us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	1.300m	82.043ms	1	1	100.00
V2	mbx_max_activity	mbx_stress_zero_delays	3.000s	472.666us	0	1	0.00
V2	mbx_imbx_oob	mbx_imbx_oob	15.000s	1.477ms	1	1	100.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	8.000s	2.832ms	1	1	100.00
V2	alert_test	mbx_alert_test	2.000s	115.595us	1	1	100.00
V2	intr_test	mbx_intr_test	10.000s	44.483us	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	11.000s	50.945us	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	11.000s	50.945us	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	10.000s	22.716us	1	1	100.00
		mbx_csr_rw	8.000s	160.539us	1	1	100.00
		mbx_csr_aliasing	7.000s	28.812us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	143.144us	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	10.000s	22.716us	1	1	100.00
		mbx_csr_rw	8.000s	160.539us	1	1	100.00
		mbx_csr_aliasing	7.000s	28.812us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	143.144us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	mbx_tl_intg_err	11.000s	172.475us	1	1	100.00
		mbx_sec_cm	2.000s	29.551us	1	1	100.00
V2S		TOTAL			2	2	100.00
		TOTAL			15	16	93.75

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:
  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.20233683361705131199216332734130033402383960266413493753533196765663482668307
      Line 159, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @ 472665778 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 472665778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---