ROM_CTRL/32KB Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.630s	319.679us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.320s	181.440us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.610s	499.358us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.470s	171.979us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	3.720s	1.164ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	5.280s	179.635us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.610s	499.358us	1	1	100.00
		rom_ctrl_csr_aliasing	3.720s	1.164ms	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.450s	169.274us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.230s	385.515us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	3.690s	411.706us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	10.680s	333.036us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	6.800s	229.753us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.840s	278.246us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.670s	604.676us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.670s	604.676us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.320s	181.440us	1	1	100.00
		rom_ctrl_csr_rw	4.610s	499.358us	1	1	100.00
		rom_ctrl_csr_aliasing	3.720s	1.164ms	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.990s	347.960us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.320s	181.440us	1	1	100.00
		rom_ctrl_csr_rw	4.610s	499.358us	1	1	100.00
		rom_ctrl_csr_aliasing	3.720s	1.164ms	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.990s	347.960us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	38.910s	1.123ms	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	19.360s	5.212ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.389m	1.708ms	1	1	100.00
		rom_ctrl_tl_intg_err	22.870s	243.256us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.389m	1.708ms	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.389m	1.708ms	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	38.910s	1.123ms	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	38.910s	1.123ms	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	38.910s	1.123ms	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	38.910s	1.123ms	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	38.910s	1.123ms	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.389m	1.708ms	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.389m	1.708ms	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.630s	319.679us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.630s	319.679us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.630s	319.679us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	22.870s	243.256us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	38.910s	1.123ms	0	1	0.00
		rom_ctrl_kmac_err_chk	6.800s	229.753us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	38.910s	1.123ms	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	38.910s	1.123ms	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	38.910s	1.123ms	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	19.360s	5.212ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.389m	1.708ms	1	1	100.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.922m	14.186ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.48420451103818867406940732844176467975859612999192033268799729660091582660798
      Line 99, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1123223649 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1123223649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---