RV_TIMER Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.650s	18.583us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.760s	14.897us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.560s	11.708us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.210s	113.673us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.720s	18.994us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.260s	39.604us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.560s	11.708us	1	1	100.00
		rv_timer_csr_aliasing	0.720s	18.994us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.400s	133.385us	0	1	0.00
V2	disabled	rv_timer_disabled	1.590s	3.776ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.886m	185.435ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.886m	185.435ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.000s	3.826ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.620s	42.470us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.630s	17.748us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.790s	42.572us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.790s	42.572us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.760s	14.897us	1	1	100.00
		rv_timer_csr_rw	0.560s	11.708us	1	1	100.00
		rv_timer_csr_aliasing	0.720s	18.994us	1	1	100.00
		rv_timer_same_csr_outstanding	1.020s	28.838us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.760s	14.897us	1	1	100.00
		rv_timer_csr_rw	0.560s	11.708us	1	1	100.00
		rv_timer_csr_aliasing	0.720s	18.994us	1	1	100.00
		rv_timer_same_csr_outstanding	1.020s	28.838us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.960s	87.697us	1	1	100.00
		rv_timer_tl_intg_err	1.200s	57.057us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.200s	57.057us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.680s	118.009us	0	1	0.00
V3	max_value	rv_timer_max	0.550s	20.242us	1	1	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	26.080s	18.519ms	0	1	0.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.106015068369529165251229020215981002448791058547369895454664648892274291462517
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 118009476 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xaff85504) == 0x1
        UVM_INFO @ 118009476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.22018331909172089633912508048868890283461901612761610918653154171446395875359
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 133384843 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x277a2104) == 0x1
        UVM_INFO @ 133384843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.21552153555019975187270375235604085930498236681803354940343782526840503597993
      Line 431, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 18518615499 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
        UVM_INFO @ 18518615499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---