SPI_DEVICE/1R1W Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	59.930s	92.393ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.090s	47.016us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.660s	61.308us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.530s	5.337ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.500s	1.285ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.340s	340.767us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.660s	61.308us	1	1	100.00
		spi_device_csr_aliasing	14.500s	1.285ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.780s	11.142us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.540s	65.577us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.810s	17.897us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.720s	7.446us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.990s	4.127us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.450s	917.786us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.450s	917.786us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.120s	553.539us	1	1	100.00
		spi_device_tpm_sts_read	0.850s	42.980us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	22.750s	19.365ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.800s	2.354ms	1	1	100.00
		spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	14.740s	8.682ms	1	1	100.00
		spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	14.740s	8.682ms	1	1	100.00
		spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.250s	150.295us	1	1	100.00
		spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.250s	150.295us	1	1	100.00
		spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.250s	150.295us	1	1	100.00
		spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.250s	150.295us	1	1	100.00
		spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.250s	150.295us	1	1	100.00
		spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	8.850s	8.682ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	10.000s	1.108ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	10.000s	1.108ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	10.000s	1.108ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	31.840s	3.826ms	1	1	100.00
		spi_device_read_buffer_direct	7.100s	3.218ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	10.000s	1.108ms	1	1	100.00
		spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	51.540s	14.833ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.870s	343.228us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.870s	343.228us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	59.930s	92.393ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.880m	190.506ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.110s	47.622us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.670s	41.423us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.820s	12.379us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.210s	408.642us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.210s	408.642us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.090s	47.016us	1	1	100.00
		spi_device_csr_rw	1.660s	61.308us	1	1	100.00
		spi_device_csr_aliasing	14.500s	1.285ms	1	1	100.00
		spi_device_same_csr_outstanding	1.470s	186.810us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.090s	47.016us	1	1	100.00
		spi_device_csr_rw	1.660s	61.308us	1	1	100.00
		spi_device_csr_aliasing	14.500s	1.285ms	1	1	100.00
		spi_device_same_csr_outstanding	1.470s	186.810us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.610s	496.669us	1	1	100.00
		spi_device_tl_intg_err	15.540s	13.163ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	15.540s	13.163ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	27.460s	4.566ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.62959788899014968290996587775124178294632490414839707253528549978780702726698
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   5778892 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[65])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   5778892 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   5778892 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[961])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.54410434414062795164573321149293522660837782888638032387826914609936907831793
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1670264 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x25dce8 [1001011101110011101000] vs 0x0 [0])
        UVM_ERROR @   1714264 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd99e9f [110110011001111010011111] vs 0x0 [0])
        UVM_ERROR @   1735264 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x91091c [100100010000100100011100] vs 0x0 [0])
        UVM_ERROR @   1824264 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdd4f55 [110111010100111101010101] vs 0x0 [0])
        UVM_ERROR @   1844264 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe4e88d [111001001110100010001101] vs 0x0 [0])