SPI_HOST Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	38.000s	4.692ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	111.481us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	17.585us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	471.584us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	34.711us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	144.276us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	17.585us	1	1	100.00
		spi_host_csr_aliasing	2.000s	34.711us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	15.940us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	174.319us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	35.912us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	153.940us	1	1	100.00
		spi_host_error_cmd	1.000s	54.582us	1	1	100.00
		spi_host_event	16.000s	1.104ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	64.971us	1	1	100.00
V2	speed	spi_host_speed	4.000s	64.971us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	64.971us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	3.000s	161.959us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	216.586us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	64.971us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	64.971us	1	1	100.00
V2	duplex	spi_host_smoke	38.000s	4.692ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	38.000s	4.692ms	1	1	100.00
V2	stress_all	spi_host_stress_all	2.000s	56.880us	1	1	100.00
V2	spien	spi_host_spien	3.000s	326.076us	1	1	100.00
V2	stall	spi_host_status_stall	14.000s	854.473us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	154.988us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	153.940us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	28.786us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	39.277us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	139.220us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	139.220us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	111.481us	1	1	100.00
		spi_host_csr_rw	1.000s	17.585us	1	1	100.00
		spi_host_csr_aliasing	2.000s	34.711us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	41.178us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	111.481us	1	1	100.00
		spi_host_csr_rw	1.000s	17.585us	1	1	100.00
		spi_host_csr_aliasing	2.000s	34.711us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	41.178us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	165.913us	1	1	100.00
		spi_host_sec_cm	1.000s	148.205us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	165.913us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	4.300m	11.679ms	1	1	100.00
		TOTAL			26	26	100.00