SRAM_CTRL/MAIN Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	56.220s	1.936ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.800s	13.052us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.880s	31.889us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.060s	30.923us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.910s	17.950us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.140s	3.122ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.880s	31.889us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	17.950us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.150m	15.060ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.882m	9.128ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.370m	64.718ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.686m	3.128ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	33.100m	191.106ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.842m	7.933ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	32.830s	8.579ms	1	1	100.00
V2	executable	sram_ctrl_executable	14.826m	25.254ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	5.770s	1.451ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.211m	71.192ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	25.970s	3.157ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	47.300s	3.285ms	1	1	100.00
		sram_ctrl_throughput_w_readback	10.040s	807.277us	1	1	100.00
V2	regwen	sram_ctrl_regwen	16.254m	364.207ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.660s	696.246us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	42.858m	620.337ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.970s	33.058us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.610s	111.524us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.610s	111.524us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.800s	13.052us	1	1	100.00
		sram_ctrl_csr_rw	0.880s	31.889us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	17.950us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.760s	15.919us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.800s	13.052us	1	1	100.00
		sram_ctrl_csr_rw	0.880s	31.889us	1	1	100.00
		sram_ctrl_csr_aliasing	0.910s	17.950us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.760s	15.919us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	31.940s	7.207ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.980s	14.174us	0	1	0.00
		sram_ctrl_tl_intg_err	2.060s	697.270us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.980s	14.174us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.060s	697.270us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	16.254m	364.207ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	16.254m	364.207ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.880s	31.889us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	14.826m	25.254ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	14.826m	25.254ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	14.826m	25.254ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	32.830s	8.579ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.950s	684.777us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	31.940s	7.207ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.010s	2.436ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	56.220s	1.936ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	56.220s	1.936ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	14.826m	25.254ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.980s	14.174us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	32.830s	8.579ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.980s	14.174us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.980s	14.174us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	56.220s	1.936ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.980s	14.174us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	30.660s	6.410ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.5541256797412161605693553409225017672234485230755134118240993402583938056126
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2436231687 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x79) != exp (0x77)
        UVM_INFO @ 2436231687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.19018074633498818076366030836851045092071501290175592403446043840418740217789
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  14174193 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  14174193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---