SRAM_CTRL/RET Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.610s	481.837us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.830s	22.645us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.850s	19.466us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.990s	607.659us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.870s	13.889us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.930s	99.635us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.850s	19.466us	1	1	100.00
		sram_ctrl_csr_aliasing	0.870s	13.889us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.400s	913.842us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.200s	193.942us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.802m	20.985ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.344m	10.448ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	56.680s	10.537ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.439m	3.758ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.610s	522.308us	1	1	100.00
V2	executable	sram_ctrl_executable	4.754m	5.401ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.460s	44.362us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.322m	58.090ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	29.740s	120.402us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	20.870s	123.891us	1	1	100.00
		sram_ctrl_throughput_w_readback	15.490s	167.575us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.383m	36.239ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.760s	43.044us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	11.945m	79.808ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.870s	18.397us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.450s	548.862us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.450s	548.862us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.830s	22.645us	1	1	100.00
		sram_ctrl_csr_rw	0.850s	19.466us	1	1	100.00
		sram_ctrl_csr_aliasing	0.870s	13.889us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.900s	71.943us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.830s	22.645us	1	1	100.00
		sram_ctrl_csr_rw	0.850s	19.466us	1	1	100.00
		sram_ctrl_csr_aliasing	0.870s	13.889us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.900s	71.943us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.680s	419.029us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.650s	5.009us	0	1	0.00
		sram_ctrl_tl_intg_err	2.600s	345.344us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.650s	5.009us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.600s	345.344us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.383m	36.239ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.383m	36.239ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.850s	19.466us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.754m	5.401ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.754m	5.401ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.754m	5.401ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.610s	522.308us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.050s	84.378us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.680s	419.029us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.000s	41.552us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.610s	481.837us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.610s	481.837us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.754m	5.401ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.650s	5.009us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.610s	522.308us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.650s	5.009us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.650s	5.009us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.610s	481.837us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.650s	5.009us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	59.560s	659.856us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.21159867198408835100638831963170553648354052131892508101183629573835876150972
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5008710 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5008710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---