UART Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: 8aa5a98

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.390s	510.833us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.640s	36.053us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.650s	13.944us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.370s	65.619us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.720s	61.867us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.820s	17.930us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.650s	13.944us	1	1	100.00
		uart_csr_aliasing	0.720s	61.867us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	30.650s	30.383ms	1	1	100.00
V2	parity	uart_smoke	1.390s	510.833us	1	1	100.00
		uart_tx_rx	30.650s	30.383ms	1	1	100.00
V2	parity_error	uart_intr	22.630s	19.883ms	1	1	100.00
		uart_rx_parity_err	1.680m	99.921ms	1	1	100.00
V2	watermark	uart_tx_rx	30.650s	30.383ms	1	1	100.00
		uart_intr	22.630s	19.883ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.149m	240.353ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	11.840s	5.074ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	30.540s	182.141ms	1	1	100.00
V2	rx_frame_err	uart_intr	22.630s	19.883ms	1	1	100.00
V2	rx_break_err	uart_intr	22.630s	19.883ms	1	1	100.00
V2	rx_timeout	uart_intr	22.630s	19.883ms	1	1	100.00
V2	perf	uart_perf	4.094m	25.601ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.900s	9.694ms	1	1	100.00
V2	line_loopback	uart_loopback	5.900s	9.694ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	8.110s	5.604ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	6.500s	39.155ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.680s	840.516us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	6.020s	3.510ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	7.944m	110.339ms	1	1	100.00
V2	stress_all	uart_stress_all	26.220s	12.836ms	1	1	100.00
V2	alert_test	uart_alert_test	0.680s	37.803us	1	1	100.00
V2	intr_test	uart_intr_test	0.700s	40.922us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.570s	71.583us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.570s	71.583us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.640s	36.053us	1	1	100.00
		uart_csr_rw	0.650s	13.944us	1	1	100.00
		uart_csr_aliasing	0.720s	61.867us	1	1	100.00
		uart_same_csr_outstanding	0.930s	109.178us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.640s	36.053us	1	1	100.00
		uart_csr_rw	0.650s	13.944us	1	1	100.00
		uart_csr_aliasing	0.720s	61.867us	1	1	100.00
		uart_same_csr_outstanding	0.930s	109.178us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.220s	329.358us	1	1	100.00
		uart_tl_intg_err	0.960s	45.708us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.960s	45.708us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	9.210s	12.735ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.50740662508270438258751786843700418199606417896997844792375473184508254294355
      Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 3291351380 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3421641380 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3421641380 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 3724421380 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 3764001380 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0