CHIP Simulation Results

Monday October 06 2025 16:04:09 UTC

GitHub Revision: `8aa5a98`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.353m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.353m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	43.283s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	15.411s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	16.182s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.696m	5.153ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.696m	5.153ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.696m	5.153ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	32.770s	10.320us	0	1	0.00
		chip_sw_example_manufacturer	2.603m		0	1	0.00
		chip_sw_example_concurrency	4.535m	5.424ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.626s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.590s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.960s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.960s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.640s	12.089us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.118m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.271m	7.670ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.277m	5.772ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	13.343s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	21.384s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.525s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	15.753s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.280s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.280s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.516m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.156m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.930m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.930m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.357m	5.276ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.538m	3.902ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.871m	14.374ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.546s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.239s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.944m	6.747ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.412m	5.852ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	23.643m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	23.643m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.340s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.328m	4.897ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.328m	4.897ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	6.496m	18.027ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.344m	4.051ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.143m	4.237ms	1	1	100.00
		chip_sw_aes_idle	4.137m	5.188ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.993m	4.644ms	1	1	100.00
		chip_sw_kmac_idle	4.395m	5.970ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.563m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.152m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.728m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.138m	11.691ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.457s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.659s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.275s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.081s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.800s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.014s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.457s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.659s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.275s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.081s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.800s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.014s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.704s		0	1	0.00
		chip_sw_aes_enc_jitter_en	38.070s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.580s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.960s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.170s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.222s		0	1	0.00
		chip_sw_clkmgr_jitter	3.613m	4.379ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.379m	4.118ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.725s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	36.790s	10.380us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	37.890s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	36.750s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.030s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	37.910s	10.240us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.422s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.568s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	14.122s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.667s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	22.190m	14.818ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	13.600m	15.715ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.328m	4.897ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.565s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	13.600m	15.715ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	15.315s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	14.205s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	19.178s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	17.296s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.878s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	22.190m	14.818ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.871m	14.374ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	22.520m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.202m	9.219ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.430m	8.534ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.968m	4.709ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	22.190m	14.818ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	15.014s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.118s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	22.190m	14.818ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	13.657s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.430m	8.534ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.858s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.319s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.418s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.029s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.575s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.484s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.118s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	13.153s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.959s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	13.153s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	13.153s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	13.153s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.762m	6.034ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.995s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.384s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	15.365s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.946s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.153s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.086m	6.290ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.538m	14.143ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.524s		0	1	0.00
		chip_prim_tl_access	8.512m	14.218ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.457s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.659s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.275s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.081s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.800s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.014s		0	1	0.00
		chip_rv_dm_lc_disabled	4.944m	6.747ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.686m	5.341ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	38.070s	10.200us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.575m	3.744ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.137m	5.188ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.007m	3.785ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	36.580s	10.340us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.993m	4.644ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.258m	4.648ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.854m	5.313ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	36.170s	10.220us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.086m	6.290ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	13.153s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	34.230s	10.300us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.469m	5.548ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.395m	5.970ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.339s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.339s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.200s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.751m	3.907ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.890s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.086m	6.290ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.960s	10.120us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	18.441s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.704s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.143m	4.237ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.143m	4.237ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.143m	4.237ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.882m	6.971ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.538m	14.143ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.538m	14.143ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.016m	10.382ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.222s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.524s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	22.190m	14.818ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.930m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	13.153s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.882m	6.971ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.086m	6.290ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.016m	10.382ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.999m	3.232ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.882m	6.971ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.086m	6.290ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.016m	10.382ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.999m	3.232ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	13.153s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.059s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.959s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.995s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.384s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	15.365s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.946s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.153s		0	1	0.00
		chip_prim_tl_access	8.512m	14.218ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.512m	14.218ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.041s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.282s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.568s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.704s		0	1	0.00
		chip_sw_aes_enc_jitter_en	38.070s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.580s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	46.960s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.170s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.222s		0	1	0.00
		chip_sw_clkmgr_jitter	3.613m	4.379ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.006m	5.661ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.006m	5.661ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.686m	5.540ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.411m	4.293ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.477m	4.373ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.041m	5.736ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.167m	5.675ms	0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.478m	5.050ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.999m	3.232ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	22.520m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	22.520m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.975m	4.160ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.466m	3.629ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.469m	5.542ms	1	1	100.00
		chip_sw_csrng_smoketest	3.502m	4.865ms	1	1	100.00
		chip_sw_gpio_smoketest	4.235m	5.116ms	1	1	100.00
		chip_sw_hmac_smoketest	4.547m	4.449ms	1	1	100.00
		chip_sw_kmac_smoketest	4.065m	4.400ms	1	1	100.00
		chip_sw_otbn_smoketest	4.407m	5.500ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.917m	4.565ms	1	1	100.00
		chip_sw_rv_plic_smoketest	4.202m	4.657ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.131m	4.189ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.246m	3.830ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.755m	5.134ms	1	1	100.00
		chip_sw_uart_smoketest	4.199m	5.087ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.403s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.626s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.118m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.132s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.889m	4.948ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.792m	5.400ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.415m	6.037ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.719m	4.129ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.243s		0	1	0.00
		chip_rv_dm_lc_disabled	4.944m	6.747ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.399s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.903s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.667s		0	1	0.00
		chip_sw_lc_walkthrough_rma	13.222s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.243s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.042s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.478s		0	1	0.00
		rom_volatile_raw_unlock	11.447s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	12.850s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	56.322s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.212m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.069m	5.147ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.069m	5.147ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.960s		0	1	0.00
		chip_same_csr_outstanding	8.620s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.960s		0	1	0.00
		chip_same_csr_outstanding	8.620s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	20.900s	21.010us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.420s	12.312us	1	1	100.00
		xbar_smoke_large_delays	4.939m	2.460ms	1	1	100.00
		xbar_smoke_slow_rsp	5.082m	1.827ms	1	1	100.00
		xbar_random_zero_delays	1.301m	71.476us	1	1	100.00
		xbar_random_large_delays	2.257m	1.206ms	1	1	100.00
		xbar_random_slow_rsp	14.712m	5.240ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.292m	163.234us	1	1	100.00
		xbar_error_and_unmapped_addr	1.633m	215.555us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	15.680s	12.761us	1	1	100.00
		xbar_error_and_unmapped_addr	1.633m	215.555us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.878m	750.196us	1	1	100.00
		xbar_access_same_device_slow_rsp	11.961m	4.218ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.311m	217.482us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	20.856m	2.910ms	1	1	100.00
		xbar_stress_all_with_error	1.745m	89.247us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	14.538m	832.171us	1	1	100.00
		xbar_stress_all_with_reset_error	20.976m	827.307us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.985s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	14.350s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.203s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.980s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	15.011s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.718s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.105s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.784s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.266s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.910s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.843s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.280s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.259s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	46.943s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	44.088s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	41.642s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	41.057s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	47.705s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	51.325s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	46.891s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	39.406s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	30.552s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	38.176s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	31.021s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	37.534s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	35.328s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	33.351s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	31.133s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.826s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.775s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.303s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.260s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.916s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.049s		0	1	0.00
		rom_e2e_asm_init_dev	12.078s		0	1	0.00
		rom_e2e_asm_init_prod	11.974s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.341s		0	1	0.00
		rom_e2e_asm_init_rma	12.569s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.863s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.287s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.674s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.674s		0	1	0.00
V2		TOTAL			64	205	31.22
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.118m	4.340ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.494m	4.001ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.211s		0	1	0.00
		rom_e2e_jtag_debug_dev	13.305s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.685s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.531s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	22.190m	14.818ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	11.914s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	19.625m	14.573ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	14.451s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.163s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.211s		0	1	0.00
		rom_e2e_jtag_debug_dev	13.305s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.685s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.047s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.765s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.790s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.677s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	24.753m	17.373ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.574m	4.636ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.764m	3.911ms	1	1	100.00
		chip_plic_all_irqs_0	9.986m	7.515ms	1	1	100.00
		chip_plic_all_irqs_10	9.642m	5.620ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.334m	5.380ms	1	1	100.00
		chip_sw_dma_abort	4.307m	4.119ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.394s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.138s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.086s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.856s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.999s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.538s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.831s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.300s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.318s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	13.265s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.800m	4.970ms	1	1	100.00
		chip_sw_mbx_smoketest	4.222m	5.365ms	1	1	100.00
		TOTAL			78	250	31.20

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.4493747073290294730632330728535053018670250826289241789204052810912006786997
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 143.675s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.35217239581643937693827848580881184904416377654699835554605862180189998868923
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 105.141s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.9373330222582681996241455223042764006710318643627581969498353487992134527774
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 80.037s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.45840495981873719947759010429692342800774529737053128293219548770327633130784
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Target //sw/device/tests:sleep_pin_retention_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 55.491s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.39145341071275254817432673674485871959849547375128681483862199086134032117732
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 67.081s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.93659201902979287234066611381417984340195923811215862765919314679453563506389
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.101879065569339074879372234983690891888059590174773031150250098442723450675298
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.52686890042836139815695613612495733655687263914247868068904375434173402766208
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.107081992144624689727062772285430794150342450643868566174544692341794890126452
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.108011923914813065703613175915933687298401416468129766023290590229054113141476
    Line 399, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 5 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.106150542789234253597436173795672688022335723747544629818921297349184192204897
Line 425, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20027.016849 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20027.016849 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.9295142222610878803079849749040768066147005413358760679327130996713126518
Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.359576 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.359576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.112330904011776333463650425476964858164438336448839001163210324455730620738930
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18026.685765 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.685765 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.82698733942633448699210676380672830633562526210864968607061674955440009521593
Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.790933 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.790933 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.51215913488457697491721404697775994108632419479313049835234282124915519283252
Line 414, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12018.433151 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.433151 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.80447583247905326261214714442832777109807422042034612538132705269800930625230
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.93085980167530400723296580782456344690486160855412902681151763544063060329068
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.37920331267315481404220791304643691341660135992379335658717498785347318735470
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.53135201600722842431848190939716470016414997503173094261526763633459764929742
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6289.884000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (12004692393636374658021435280171464659570042551949135432738651380643232276592740489603733530494484479131821063636919250166195870565912364459130263655767132 [0xe535b6d0aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3636306217f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 6289.884000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.14697994083138999102629933753384746753107358653573622293819192017346574311849
Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6033.589400 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (5041880069043472270652078655832297115311809941449874596817141585514923513665426852927845017734234245815052113026247067981351425388959226897435777730698332 [0x60443248aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3e61282b97f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 6033.589400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.32390274076027771678931651512191985231529584972730463885944684921068698832855
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5276.083410 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'haad58f64  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h0  a_user: 'h2697d  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5276.083410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.43179465990474359467245052069031468063585960205381157507847177462585931257145
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3901.863859 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'he81ab5b0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h0  a_user: 'h26966  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3901.863859 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.821309711670389852119391324274920535097479694096207041563145419502691966060
    Line 1378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.46761759054830749204666414284351705881757218980014214518631712882038764062576
    Line 422, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5772.377410 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5772.377410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.87536241996413684665972176730040415122696622686640684623919453034979170384713
    Line 634, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8534.484574 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8534.484574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.59130829687769486417529775859098096641046680226471769781065457763348607789337
    Line 407, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5539.679096 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5539.679096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.68569766393619319018697365864826952106405937865349308496669188989927448653550
    Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4293.419737 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4293.419737 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.43257924937746402734930289272588916124093936696151322148098350809869014533088
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4896.759744 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4896.759744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 0.chip_sw_rv_core_ibex_rnd.19778595537511244422700996236906619697014113062928497822338116209975256168950
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 5674.973850 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 5674.973850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.92522477687525201091185813117955453547116872540679659256773195608071884425584
    Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5736.231056 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5736.231056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.68720868831706407608515065392696640939829438133607663157870856978646114702812
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.23016591982508785405039720850129536873355024873314632869817109174471081519413
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5147.047368 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5147.047368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.74430906501955705868458391204636440571655253200937570275000848185702680091013
    Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.667520 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.667520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.60138769428575075853790107632801169040798006650177579257028913697886330202486
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14373.843668 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14373.843668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.82565671305188065324867904511738917782463372000311111428950869634011135972373
    Line 224, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 6746.809527 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40544 read out mismatch
  UVM_INFO @ 6746.809527 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.77069645718019490287620884011823520429012617652065230373953420949187631213521
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.1605101139021445419868859013740379558257112978296682252781900358032757436206
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4119.193908 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4119.193908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```