| V1 |
smoke |
aon_timer_smoke |
0.960s |
524.010us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
1.010s |
1.244ms |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
0.920s |
383.037us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
8.800s |
7.823ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
1.210s |
427.326us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
1.030s |
450.787us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
0.920s |
383.037us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.210s |
427.326us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
1.160s |
372.483us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
0.730s |
487.625us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
23.640s |
41.679ms |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
0.800s |
523.825us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
48.810s |
48.394ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
0.840s |
393.792us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
0.860s |
349.697us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
1.580s |
668.653us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
1.580s |
668.653us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
1.010s |
1.244ms |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.920s |
383.037us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.210s |
427.326us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
3.150s |
2.498ms |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
1.010s |
1.244ms |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
0.920s |
383.037us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
1.210s |
427.326us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
3.150s |
2.498ms |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
2.880s |
7.408ms |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
10.890s |
8.531ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
10.890s |
8.531ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
0.750s |
542.228us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
1.490s |
473.809us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
5.330s |
3.737ms |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
0.890s |
628.859us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
3.900s |
4.253ms |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
12.510s |
7.818ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |