CSRNG Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	3.000s	17.462us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	2.000s	52.275us	1	1	100.00
V1	csr_rw	csrng_csr_rw	2.000s	22.094us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	15.000s	585.145us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	336.648us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	2.000s	36.663us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	2.000s	22.094us	1	1	100.00
		csrng_csr_aliasing	6.000s	336.648us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	4.000s	54.754us	0	1	0.00
V2	alerts	csrng_alert	9.000s	315.769us	1	1	100.00
V2	err	csrng_err	2.000s	48.342us	1	1	100.00
V2	cmds	csrng_cmds	43.000s	4.499ms	1	1	100.00
V2	life cycle	csrng_cmds	43.000s	4.499ms	1	1	100.00
V2	stress_all	csrng_stress_all	1.267m	4.444ms	1	1	100.00
V2	intr_test	csrng_intr_test	3.000s	67.858us	1	1	100.00
V2	alert_test	csrng_alert_test	2.000s	18.473us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	5.000s	226.268us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	5.000s	226.268us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	2.000s	52.275us	1	1	100.00
		csrng_csr_rw	2.000s	22.094us	1	1	100.00
		csrng_csr_aliasing	6.000s	336.648us	1	1	100.00
		csrng_same_csr_outstanding	3.000s	90.320us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	2.000s	52.275us	1	1	100.00
		csrng_csr_rw	2.000s	22.094us	1	1	100.00
		csrng_csr_aliasing	6.000s	336.648us	1	1	100.00
		csrng_same_csr_outstanding	3.000s	90.320us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	3.000s	232.443us	1	1	100.00
		csrng_tl_intg_err	5.000s	398.610us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	1.000s	22.024us	1	1	100.00
		csrng_csr_rw	2.000s	22.094us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	9.000s	315.769us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1.267m	4.444ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
		csrng_sec_cm	3.000s	232.443us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
		csrng_sec_cm	3.000s	232.443us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
		csrng_sec_cm	3.000s	232.443us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
		csrng_sec_cm	3.000s	232.443us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
		csrng_sec_cm	3.000s	232.443us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
		csrng_sec_cm	3.000s	232.443us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
		csrng_sec_cm	3.000s	232.443us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	9.000s	315.769us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1.267m	4.444ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	9.000s	315.769us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	5.000s	398.610us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
		csrng_sec_cm	3.000s	232.443us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
		csrng_sec_cm	3.000s	232.443us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	4.000s	54.754us	0	1	0.00
		csrng_err	2.000s	48.342us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.867m	7.381ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed has 1 failures:
  • Test csrng_intr has 1 failures.

    • 0.csrng_intr.39706433216540102708925288236050665100613178069409394616970618115490053342426
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 54754344 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  54754344 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  54754344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---