DMA Simulation Results

Tuesday October 07 2025 16:07:43 UTC

GitHub Revision: 0f6fcf0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	4.000s	1.407ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	997.454us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	4.000s	1.099ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	94.947us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	20.420us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	10.000s	293.824us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	581.273us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	1.000s	50.900us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	20.420us	1	1	100.00
		dma_csr_aliasing	6.000s	581.273us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	46.000s	8.832ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	15.467m	78.755ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	7.750m	86.464ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	7.750m	86.464ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	15.467m	78.755ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	1.767m	30.332ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	7.750m	86.464ms	1	1	100.00
V2	dma_abort	dma_abort	5.000s	583.056us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.283m	47.301ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	15.561us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	37.821us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	133.908us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	133.908us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	94.947us	1	1	100.00
		dma_csr_rw	2.000s	20.420us	1	1	100.00
		dma_csr_aliasing	6.000s	581.273us	1	1	100.00
		dma_same_csr_outstanding	2.000s	66.711us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	94.947us	1	1	100.00
		dma_csr_rw	2.000s	20.420us	1	1	100.00
		dma_csr_aliasing	6.000s	581.273us	1	1	100.00
		dma_same_csr_outstanding	2.000s	66.711us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	14.000s	454.850us	1	1	100.00
		dma_generic_stress	1.767m	30.332ms	1	1	100.00
		dma_handshake_stress	7.750m	86.464ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	11.000s	556.842us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	2.000s	188.865us	1	1	100.00
		dma_sec_cm	1.000s	37.591us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.783m	77.567ms	1	1	100.00
		dma_longer_transfer	2.000s	264.300us	1	1	100.00
		dma_stress_all_with_rand_reset	3.000s	113.107us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.61132631695973748305784085796106627797361147145876186352946624450829087388457
      Line 87, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  113107080ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  113107080ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---